diff --git a/MAINTAINERS b/MAINTAINERS
index c77abba..aa4b3bc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -74,6 +74,13 @@
 F:	doc/device-tree-bindings/gpio/snps,creg-gpio.txt
 F:	drivers/gpio/hsdk-creg-gpio.c
 
+ARC SYNOPSYS DW MMC EXTENSIONS
+M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S:	Maintained
+L:	uboot-snps-arc@synopsys.com
+F:	doc/device-tree-bindings/mmc/snps,dw-mmc.txt
+F:	drivers/mmc/snps_dw_mmc.c
+
 ARM
 M:	Albert Aribaud <albert.u.boot@aribaud.net>
 S:	Maintained
diff --git a/Makefile b/Makefile
index 2824a6e..66a09ac 100644
--- a/Makefile
+++ b/Makefile
@@ -1052,8 +1052,13 @@
 	-a 0 -e 0 -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
 
+ifneq ($(EXT_DTB),)
+u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB)
+		$(call if_changed,cat)
+else
 u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER)
 	$(call if_changed,cat)
+endif
 
 u-boot.bin: u-boot-fit-dtb.bin FORCE
 	$(call if_changed,copy)
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index b5aacd5..6d97de9 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -31,6 +31,25 @@
 				#clock-cells = <0>;
 				u-boot,dm-pre-reloc;
 			};
+
+			mmcclk_ciu: mmcclk-ciu {
+				compatible = "fixed-clock";
+				/*
+				 * DW sdio controller has external ciu clock divider
+				 * controlled via register in SDIO IP. It divides
+				 * sdio_ref_clk (which comes from CGU) by 16 for
+				 * default. So default mmcclk clock (which comes
+				 * to sdk_in) is 25000000 Hz.
+				 */
+				clock-frequency = <25000000>;
+				#clock-cells = <0>;
+			};
+
+			mmcclk_biu: mmcclk-biu {
+				compatible = "fixed-clock";
+				clock-frequency = <50000000>;
+				#clock-cells = <0>;
+			};
 		};
 
 		ethernet@18000 {
@@ -53,6 +72,15 @@
 			reg = < 0x60000 0x100 >;
 		};
 
+		mmc: mmc@15000 {
+			compatible = "snps,dw-mshc";
+			reg = <0x15000 0x400>;
+			bus-width = <4>;
+			clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+			clock-names = "biu", "ciu";
+			max-frequency = <25000000>;
+		};
+
 		uart0: serial0@22000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x22000 0x100>;
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 5e9ba05..7028050 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -86,6 +86,32 @@
 		reg = <0xf0060000 0x100>;
 	};
 
+	mmcclk_ciu: mmcclk-ciu {
+		compatible = "fixed-clock";
+		/*
+		 * DW sdio controller has external ciu clock divider
+		 * controlled via register in SDIO IP. Due to its
+		 * unexpected default value (it should divide by 1
+		 * but it divides by 8) SDIO IP uses wrong clock and
+		 * works unstable (see STAR 9001204800)
+		 * We switched to the minimum possible value of the
+		 * divisor (div-by-2) in HSDK platform code.
+		 * So default mmcclk ciu clock is 50000000 Hz.
+		 */
+		clock-frequency = <50000000>;
+		#clock-cells = <0>;
+	};
+
+	mmc: mmc0@f000a000 {
+		compatible = "snps,dw-mshc";
+		reg = <0xf000a000 0x400>;
+		bus-width = <4>;
+		fifo-depth = <256>;
+		clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
+		clock-names = "biu", "ciu";
+		max-frequency = <25000000>;
+	};
+
 	spi0: spi@f0020000 {
 		compatible = "snps,dw-apb-ssi";
 		reg = <0xf0020000 0x1000>;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4640f3b..f58f8fb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -857,6 +857,8 @@
 	select DM_ETH
 	select DM_GPIO
 	select DM_KEYBOARD
+	select DM_MMC if MMC
+	select DM_SCSI if SCSI
 	select DM_SERIAL
 	select DM_USB if DISTRO_DEFAULTS
 	select OF_BOARD_SETUP
diff --git a/arch/arm/cpu/armv7/vf610/Kconfig b/arch/arm/cpu/armv7/vf610/Kconfig
index 13905b5..5d485a3 100644
--- a/arch/arm/cpu/armv7/vf610/Kconfig
+++ b/arch/arm/cpu/armv7/vf610/Kconfig
@@ -23,6 +23,7 @@
 	bool "BK4r1"
 	select SYS_FSL_ERRATUM_ESDHC135
 	select SYS_FSL_ERRATUM_ESDHC_A001
+	select BOARD_LATE_INIT
 
 endchoice
 
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index cbd3391..90fa695 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -252,7 +252,7 @@
 );
 
 #ifdef CONFIG_FEC_MXC
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+__weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 	struct fuse_bank *bank = &ocotp->bank[4];
@@ -375,3 +375,25 @@
 	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
 }
 #endif
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be from 0 - 3 */
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+
+	switch (i2c_num) {
+	case 0:
+		clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,
+				CCM_CCGR4_I2C0_CTRL_MASK);
+	case 2:
+		clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
+				CCM_CCGR10_I2C2_CTRL_MASK);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9bcff7d..5fe9989 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -492,16 +492,20 @@
 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 	vf610-colibri.dtb \
 	vf610-twr.dtb \
-	pcm052.dtb \
-	bk4r1.dtb
+	vf610-pcm052.dtb \
+	vf610-bk4r1.dtb
 
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
 	imx53-kp.dtb
 
 dtb-$(CONFIG_MX6Q) += \
+	imx6-apalis.dtb \
 	imx6q-display5.dtb \
 	imx6q-logicpd.dtb
 
+dtb-$(CONFIG_TARGET_TBS2910) += \
+	imx6q-tbs2910.dtb
+
 dtb-$(CONFIG_MX6QDL) += \
 	imx6dl-icore.dtb \
 	imx6dl-icore-mipi.dtb \
@@ -518,6 +522,9 @@
 	imx6qp-sabreauto.dtb \
 	imx6qp-sabresd.dtb
 
+dtb-$(CONFIG_TARGET_WANDBOARD) += \
+	imx6dl-wandboard-revb1.dtb
+
 dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
 
 dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb
@@ -543,6 +550,9 @@
 	imx6ull-14x14-evk.dtb \
 	imx6ull-colibri.dtb \
 
+dtb-$(CONFIG_ARCH_MX6) += \
+	imx6-colibri.dtb
+
 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 	imx7d-sdb-qspi.dtb \
 	imx7-colibri-emmc.dtb \
@@ -702,6 +712,9 @@
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt7629-rfb.dtb
 
+dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
+dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here
diff --git a/arch/arm/dts/am57xx-cl-som-am57x.dts b/arch/arm/dts/am57xx-cl-som-am57x.dts
deleted file mode 100644
index 203266f..0000000
--- a/arch/arm/dts/am57xx-cl-som-am57x.dts
+++ /dev/null
@@ -1,617 +0,0 @@
-/*
- * Support for CompuLab CL-SOM-AM57x System-on-Module
- *
- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "dra74x.dtsi"
-
-/ {
-	model = "CompuLab CL-SOM-AM57x";
-	compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&leds_pins_default>;
-
-		led0 {
-			label = "cl-som-am57x:green";
-			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-	};
-
-	vdd_3v3: fixedregulator-vdd_3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	ads7846reg: fixedregulator-ads7846-reg {
-		compatible = "regulator-fixed";
-		regulator-name = "ads7846-reg";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	sound0: sound0 {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,bitclock-master = <&dailink0_master>;
-		simple-audio-card,frame-master = <&dailink0_master>;
-		simple-audio-card,widgets =
-					"Headphone", "Headphone Jack",
-					"Microphone", "Microphone Jack",
-					"Line", "Line Jack";
-		simple-audio-card,routing =
-					"Headphone Jack", "RHPOUT",
-					"Headphone Jack", "LHPOUT",
-					"LLINEIN", "Line Jack",
-					"MICIN", "Mic Bias",
-					"Mic Bias", "Microphone Jack";
-
-		dailink0_master: simple-audio-card,cpu {
-			sound-dai = <&mcasp3>;
-		};
-
-		simple-audio-card,codec {
-			sound-dai = <&wm8731>;
-			system-clock-frequency = <12000000>;
-		};
-	};
-};
-
-&dra7_pmx_core {
-	leds_pins_default: leds_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14)	/* gpmc_a15.gpio2_5 */
-		>;
-	};
-
-	i2c1_pins_default: i2c1_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda.sda */
-			DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl.scl */
-		>;
-	};
-
-	i2c3_pins_default: i2c3_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10)	/* mcasp1_aclkx.i2c3_sda */
-			DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10)	/* mcasp1_fsx.i2c3_scl */
-		>;
-	};
-
-	i2c4_pins_default: i2c4_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10)	/* mcasp1_acl.i2c4_sda */
-			DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10)	/* mcasp1_fsr.i2c4_scl */
-		>;
-	};
-
-	tps659038_pins_default: tps659038_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
-		>;
-	};
-
-	mmc2_pins_default: mmc2_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
-			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
-			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
-			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
-			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
-			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
-			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
-			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
-			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
-			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
-		>;
-	};
-
-	qspi1_pins: pinmux_qspi1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1)	/* gpmc_a13.qspi1_rtclk */
-			DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1)	/* gpmc_a16.qspi1_d0 */
-			DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)	/* gpmc_a17.qspi1_d1 */
-			DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1)	/* qpmc_a18.qspi1_sclk */
-			DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_cs2.qspi1_cs0 */
-			DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_cs3.qspi1_cs1 */
-		>;
-	};
-
-	cpsw_pins_default: cpsw_pins_default {
-		pinctrl-single,pins = <
-			/* Slave at addr 0x0 */
-			DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)	/* rgmii0_tclk */
-			DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)	/* rgmii0_tctl */
-			DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)	/* rgmii0_td3 */
-			DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)	/* rgmii0_td2 */
-			DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)	/* rgmii0_td1 */
-			DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)	/* rgmii0_td0 */
-			DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */
-			DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */
-			DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */
-			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */
-			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */
-			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */
-
-			/* Slave at addr 0x1 */
-			DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d12.rgmii1_tclk */
-			DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d13.rgmii1_tctl */
-			DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d14.rgmii1_td3 */
-			DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d15.rgmii1_td2 */
-			DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d16.rgmii1_td1 */
-			DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d17.rgmii1_td0 */
-			DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
-			DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
-			DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
-			DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
-			DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
-			DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
-		>;
-	};
-
-	cpsw_pins_sleep: cpsw_pins_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
-
-			/* Slave 2 */
-			DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
-		>;
-	};
-
-	davinci_mdio_pins_default: davinci_mdio_pins_default {
-		pinctrl-single,pins = <
-			/* MDIO */
-			DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */
-			DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3)	/* vin2a_d11.mdio_d */
-		>;
-	};
-
-	davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15)
-		>;
-	};
-
-	ads7846_pins: pinmux_ads7846_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */
-		>;
-	};
-
-	mcasp3_pins_default: mcasp3_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
-			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
-			DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
-			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
-		>;
-	};
-
-	mcasp3_pins_sleep: mcasp3_pins_sleep {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
-		>;
-	};
-};
-
-&i2c1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&i2c3 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c3_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&i2c4 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c4_pins_default>;
-	clock-frequency = <400000>;
-
-	tps659038: tps659038@58 {
-		compatible = "ti,tps659038";
-		reg = <0x58>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&tps659038_pins_default>;
-
-		#interrupt-cells = <2>;
-		interrupt-controller;
-
-		ti,system-power-controller;
-
-		tps659038_pmic {
-			compatible = "ti,tps659038-pmic";
-
-			regulators {
-				smps12_reg: smps12 {
-					/* VDD_MPU */
-					regulator-name = "smps12";
-					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps3_reg: smps3 {
-					/* VDD_DDR */
-					regulator-name = "smps3";
-					regulator-min-microvolt = <1500000>;
-					regulator-max-microvolt = <1500000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps45_reg: smps45 {
-					/* VDD_DSPEVE */
-					regulator-name = "smps45";
-					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps6_reg: smps6 {
-					/* VDD_GPU */
-					regulator-name = "smps6";
-					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps7_reg: smps7 {
-					/* VDD_CORE */
-					regulator-name = "smps7";
-					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1160000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps8_reg: smps8 {
-					/* VDD_IVA */
-					regulator-name = "smps8";
-					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps9_reg: smps9 {
-					/* PMIC_3V3 */
-					regulator-name = "smps9";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-
-				ldo1_reg: ldo1 {
-					/* VDD_SD / VDDSHV8  */
-					regulator-name = "ldo1";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				ldo2_reg: ldo2 {
-					/* VDD_1V8 */
-					regulator-name = "ldo2";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo3_reg: ldo3 {
-					/* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */
-					regulator-name = "ldo3";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo4_reg: ldo4 {
-					/* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */
-					regulator-name = "ldo4";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo9_reg: ldo9 {
-					/* VDD_RTC */
-					regulator-name = "ldo9";
-					regulator-min-microvolt = <1050000>;
-					regulator-max-microvolt = <1050000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldoln_reg: ldoln {
-					/* VDDA_1V8_PLL */
-					regulator-name = "ldoln";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldousb_reg: ldousb {
-					/* VDDA_3V_USB: VDDA_USBHS33 */
-					regulator-name = "ldousb";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				/* regen1 not used */
-			};
-		};
-
-		tps659038_pwr_button: tps659038_pwr_button {
-			compatible = "ti,palmas-pwrbutton";
-			interrupt-parent = <&tps659038>;
-			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-			wakeup-source;
-			ti,palmas-long-press-seconds = <12>;
-		};
-
-		tps659038_gpio: tps659038_gpio {
-			compatible = "ti,palmas-gpio";
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-	};
-
-	rtc0: rtc@56 {
-		compatible = "emmicro,em3027";
-		reg = <0x56>;
-	};
-
-	eeprom_module: atmel@50 {
-		compatible = "atmel,24c08";
-		reg = <0x50>;
-		pagesize = <16>;
-	};
-
-	wm8731: wm8731@1a {
-		#sound-dai-cells = <0>;
-		compatible = "wlf,wm8731";
-		reg = <0x1a>;
-		status = "okay";
-	};
-};
-
-&cpu0 {
-	cpu0-supply = <&smps12_reg>;
-	voltage-tolerance = <1>;
-};
-
-&sata {
-	status = "okay";
-};
-
-&mailbox5 {
-	status = "okay";
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
-		status = "okay";
-	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
-		status = "okay";
-	};
-};
-
-&mailbox6 {
-	status = "okay";
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
-		status = "okay";
-	};
-	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
-		status = "okay";
-	};
-};
-
-&mmc2 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_default>;
-
-	vmmc-supply = <&vdd_3v3>;
-	bus-width = <8>;
-	ti,non-removable;
-	cap-mmc-dual-data-rate;
-};
-
-&qspi {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&qspi1_pins>;
-
-	spi-max-frequency = <48000000>;
-
-	spi_flash: spi_flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spansion,m25p80", "jedec,spi-nor";
-		reg = <0>;				/* CS0 */
-		spi-max-frequency = <48000000>;
-
-		partition@0 {
-			label = "uboot";
-			reg = <0x0 0xc0000>;
-		};
-
-		partition@c0000 {
-			label = "uboot environment";
-			reg = <0xc0000 0x40000>;
-		};
-
-		partition@100000 {
-			label = "reserved";
-			reg = <0x100000 0x0>;
-		};
-	};
-
-	/* touch controller */
-	ads7846@0 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&ads7846_pins>;
-
-		compatible = "ti,ads7846";
-		vcc-supply = <&ads7846reg>;
-
-		reg = <1>;                              /* CS1 */
-		spi-max-frequency = <1500000>;
-
-		interrupt-parent = <&gpio1>;
-		interrupts = <31 0>;
-		pendown-gpio = <&gpio1 31 0>;
-
-
-		ti,x-min = /bits/ 16 <0x0>;
-		ti,x-max = /bits/ 16 <0x0fff>;
-		ti,y-min = /bits/ 16 <0x0>;
-		ti,y-max = /bits/ 16 <0x0fff>;
-
-		ti,x-plate-ohms = /bits/ 16 <180>;
-		ti,pressure-max = /bits/ 16 <255>;
-
-		ti,debounce-max = /bits/ 16 <30>;
-		ti,debounce-tol = /bits/ 16 <10>;
-		ti,debounce-rep = /bits/ 16 <1>;
-
-		wakeup-source;
-	};
-};
-
-&mac {
-	status = "okay";
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_pins_default>;
-	pinctrl-1 = <&cpsw_pins_sleep>;
-	dual_emac;
-};
-
-&cpsw_emac0 {
-	phy_id = <&davinci_mdio>, <0>;
-	phy-mode = "rgmii-txid";
-	dual_emac_res_vlan = <0>;
-};
-
-&cpsw_emac1 {
-	phy_id = <&davinci_mdio>, <1>;
-	phy-mode = "rgmii-txid";
-	dual_emac_res_vlan = <1>;
-};
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_pins_default>;
-	pinctrl-1 = <&davinci_mdio_pins_sleep>;
-};
-
-&usb2_phy1 {
-	phy-supply = <&ldousb_reg>;
-};
-
-&usb2_phy2 {
-	phy-supply = <&ldousb_reg>;
-};
-
-&usb1 {
-	dr_mode = "host";
-};
-
-&usb2 {
-	dr_mode = "host";
-};
-
-&mcasp3 {
-	#sound-dai-cells = <0>;
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&mcasp3_pins_default>;
-	pinctrl-1 = <&mcasp3_pins_sleep>;
-	status = "okay";
-
-	op-mode = <0>;	/* MCASP_IIS_MODE */
-	tdm-slots = <2>;
-	/* 4 serializers */
-	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
-		1 2 0 0
-	>;
-};
-
-&gpio3 {
-	status = "okay";
-	ti,no-reset-on-init;
-};
-
-&gpio2 {
-	status = "okay";
-	ti,no-reset-on-init;
-};
diff --git a/arch/arm/dts/am57xx-sbc-am57x.dts b/arch/arm/dts/am57xx-sbc-am57x.dts
deleted file mode 100644
index 31f9be6..0000000
--- a/arch/arm/dts/am57xx-sbc-am57x.dts
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Support for CompuLab SBC-AM57x single board computer
- *
- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-#include "am57xx-cl-som-am57x.dts"
-#include "compulab-sb-som.dtsi"
-
-/ {
-	model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
-	compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
-
-	aliases {
-		display0 = &lcd0;
-		display1 = &hdmi;
-	};
-};
-
-&dra7_pmx_core {
-	uart3_pins_default: uart3_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0)	/* uart3_rxd */
-			DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0)	/* uart3_txd */
-		>;
-	};
-
-	mmc1_pins_default: mmc1_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
-			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
-			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
-			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
-			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
-			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
-			DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)	/* mmc1_sdcd.gpio6_27 */
-			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14)	/* mmc1_sdwp.gpio6_28 */
-		>;
-	};
-
-	usb1_pins: pinmux_usb1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
-		>;
-	};
-
-	i2c5_pins_default: i2c5_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10)	/* mcasp1_axr0.i2c5_sda */
-			DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10)	/* mcasp1_axr1.i2c5_scl */
-		>;
-	};
-
-	lcd_pins_default: lcd_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14)      /* vin2a_vsync0.gpio4_0 */
-		>;
-	};
-
-	hdmi_pins: pinmux_hdmi_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1)	/* i2c2_sda.hdmi1_ddc_scl */
-			DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1)	/* i2c2_scl.hdmi1_ddc_sda */
-		>;
-	};
-
-	hdmi_conn_pins: pinmux_hdmi_conn_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14)	/* spi1_cs2.gpio7_12 */
-		>;
-	};
-};
-
-&uart3 {
-	status = "okay";
-	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
-			      <&dra7_pmx_core 0x3f8>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins_default>;
-};
-
-&mmc1 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins_default>;
-
-	vmmc-supply = <&ldo1_reg>;
-	bus-width = <4>;
-	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
-};
-
-&usb1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb1_pins>;
-};
-
-&i2c5 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c5_pins_default>;
-	clock-frequency = <400000>;
-
-	eeprom_base: atmel@54 {
-		compatible = "atmel,24c08";
-		reg = <0x54>;
-		pagesize = <16>;
-	};
-
-	pca9555: pca9555@20 {
-		compatible = "nxp,pca9555";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&dss {
-	status = "ok";
-
-	vdda_video-supply = <&ldoln_reg>;
-
-	port {
-		dpi_lcd_out: endpoint {
-			remote-endpoint = <&lcd_in>;
-			data-lines = <24>;
-		};
-	};
-};
-
-&lcd0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&lcd_pins_default>;
-
-	enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH
-			&gpio4 0 GPIO_ACTIVE_HIGH>;
-
-	port {
-		lcd_in: endpoint {
-			remote-endpoint = <&dpi_lcd_out>;
-			data-lines = <24>;
-		};
-	};
-};
-
-&hdmi {
-	status = "ok";
-	vdda-supply = <&ldo4_reg>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&hdmi_pins>;
-
-	port {
-		hdmi_out: endpoint {
-			remote-endpoint = <&hdmi_connector_in>;
-			lanes = <1 0 3 2 5 4 7 6>;
-		};
-	};
-};
-
-&hdmi_conn {
-	pinctrl-names = "default";
-	pinctrl-0 = <&hdmi_conn_pins>;
-
-	hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
-
-	port {
-		hdmi_connector_in: endpoint {
-			remote-endpoint = <&hdmi_out>;
-		};
-	};
-};
diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts
deleted file mode 100644
index 16c6026..0000000
--- a/arch/arm/dts/bk4r1.dts
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2016 Toradex AG
- */
-
-/dts-v1/;
-#include "vf.dtsi"
-
-/ {
-	model = "Phytec phyCORE-Vybrid";
-	compatible = "phytec,pcm052", "fsl,vf610";
-
-	chosen {
-		stdout-path = &uart1;
-	};
-
-	aliases {
-		spi0 = &qspi0;
-	};
-
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&qspi0 {
-	bus-num = <0>;
-	num-cs = <2>;
-	status = "okay";
-
-	qflash0: spi_flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <108000000>;
-		reg = <0>;
-	};
-
-	qflash1: spi_flash@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <66000000>;
-		reg = <1>;
-	};
-};
diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts
new file mode 100644
index 0000000..f89d6f4
--- /dev/null
+++ b/arch/arm/dts/imx53-ppd.dts
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR X11 */
+/*
+ * Copyright 2018 General Electric Company
+ * Based on imx53-ppd.dts from kernel 4.20.5.
+ */
+
+/dts-v1/;
+
+#include "imx53.dtsi"
+
+/ {
+	model = "General Electric CS ONE";
+	compatible = "ge,imx53-cpuvo", "fsl,imx53";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_esdhc3: esdhc3grp {
+		fsl,pins = <
+			MX53_PAD_PATA_DATA8__ESDHC3_DAT0        0x1d5
+			MX53_PAD_PATA_DATA9__ESDHC3_DAT1        0x1d5
+			MX53_PAD_PATA_DATA10__ESDHC3_DAT2       0x1d5
+			MX53_PAD_PATA_DATA11__ESDHC3_DAT3       0x1d5
+			MX53_PAD_PATA_DATA0__ESDHC3_DAT4        0x1d5
+			MX53_PAD_PATA_DATA1__ESDHC3_DAT5        0x1d5
+			MX53_PAD_PATA_DATA2__ESDHC3_DAT6        0x1d5
+			MX53_PAD_PATA_DATA3__ESDHC3_DAT7        0x1d5
+			MX53_PAD_PATA_RESET_B__ESDHC3_CMD       0x1d5
+			MX53_PAD_PATA_IORDY__ESDHC3_CLK         0x1d5
+		>;
+	};
+};
+
+/* eMMC */
+&esdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc3>;
+	compatible = "fsl,esdhc";
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index e13009c..0fd4acc 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -33,6 +33,8 @@
 		i2c2 = &i2c3;
 		mmc0 = &esdhc1;
 		mmc1 = &esdhc2;
+		mmc2 = &esdhc3;
+		mmc3 = &esdhc4;
 	};
 
 	tzic: tz-interrupt-controller@fffc000 {
@@ -86,6 +88,30 @@
 					bus-width = <4>;
 					status = "disabled";
 				};
+
+				esdhc3: esdhc@50020000 {
+					compatible = "fsl,imx53-esdhc";
+					reg = <0x50020000 0x4000>;
+					interrupts = <3>;
+					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
+						 <&clks IMX5_CLK_DUMMY>,
+						 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+					clock-names = "ipg", "ahb", "per";
+					bus-width = <4>;
+					status = "disabled";
+				};
+
+				esdhc4: esdhc@50024000 {
+					compatible = "fsl,imx53-esdhc";
+					reg = <0x50024000 0x4000>;
+					interrupts = <4>;
+					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
+						 <&clks IMX5_CLK_DUMMY>,
+						 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+					clock-names = "ipg", "ahb", "per";
+					bus-width = <4>;
+					status = "disabled";
+				};
 			};
 
 			iomuxc: iomuxc@53fa8000 {
diff --git a/arch/arm/dts/imx6-apalis.dts b/arch/arm/dts/imx6-apalis.dts
new file mode 100644
index 0000000..b2fdfa1
--- /dev/null
+++ b/arch/arm/dts/imx6-apalis.dts
@@ -0,0 +1,730 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6q.dtsi"
+
+/ {
+	model = "Toradex Apalis iMX6Q/D";
+	compatible = "toradex,apalis_imx6q", "fsl,imx6q";
+
+	/* Will be filled by the bootloader */
+	memory@10000000 {
+		device_type = "memory";
+		reg = <0x10000000 0>;
+	};
+
+	aliases {
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc1;
+		mmc2 = &usdhc2;
+		usb0 = &usbotg; /* required for ums */
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	reg_module_3v3: regulator-module-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* USBO1_EN */
+		enable-active-high;
+	};
+
+	/* on-module USB hub */
+	reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
+		regulator-name = "usb_host_vbus_hub";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <2000>;
+		enable-active-high;
+	};
+
+	reg_usb_host_vbus: regulator-usb-host-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
+		regulator-name = "usb_host_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* USBH_EN */
+		enable-active-high;
+		vin-supply = <&reg_usb_host_vbus_hub>;
+	};
+};
+
+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+/*
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
+ */
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_recovery>;
+	scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+/* Apalis Serial ATA */
+&sata {
+	status = "okay";
+};
+
+/* Apalis UART1 */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
+	fsl,dte-mode;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Apalis UART2 */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_dte>;
+	fsl,dte-mode;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Apalis UART3 */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4_dte>;
+	fsl,dte-mode;
+	status = "okay";
+};
+
+/* Apalis UART4 */
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5_dte>;
+	fsl,dte-mode;
+	status = "okay";
+};
+
+/* Apalis USBH[2|3|4] */
+&usbh1 {
+	dr_mode = "host";
+	vbus-supply = <&reg_usb_host_vbus>;
+	status = "okay";
+};
+
+/* Apalis USBO1 */
+&usbotg {
+	dr_mode = "host";
+	vbus-supply = <&reg_usb_otg_vbus>;
+	status = "okay";
+};
+
+/* Apalis MMC1 */
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
+	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; /* MMC1_CD */
+	disable-wp;
+	no-1-8-v;
+	status = "okay";
+};
+
+/* Apalis SD1 */
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;	/* SD1_CD */
+	disable-wp;
+	no-1-8-v;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	vqmmc-supply = <&reg_module_3v3>;
+	bus-width = <8>;
+	no-1-8-v;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_apalis_gpio1: gpio2io04grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D4__GPIO2_IO04	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio2: gpio2io05grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D5__GPIO2_IO05	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio3: gpio2io06grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D6__GPIO2_IO06	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio4: gpio2io07grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D7__GPIO2_IO07	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio5: gpio6io10grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio6: gpio6io09grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio7: gpio1io02grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio8: gpio1io06grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x130b0
+		>;
+	};
+
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC	0x130b0
+			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD	0x130b0
+			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS	0x130b0
+			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD	0x130b0
+			/* SGTL5000 sys_mclk */
+			MX6QDL_PAD_GPIO_5__CCM_CLKO1		0x130b0
+		>;
+	};
+
+	pinctrl_cam_mclk: cammclkgrp {
+		fsl,pins = <
+			/* CAM sys_mclk */
+			MX6QDL_PAD_NANDF_CS2__CCM_CLKO2	0x00b0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO	0x100b1
+			MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI	0x100b1
+			MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK	0x100b1
+			/* SPI1 cs */
+			MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25	0x000b1
+		>;
+	};
+
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
+			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
+			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
+			/* SPI2 cs */
+			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x000b1
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			/* Ethernet PHY reset */
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x000b0
+			/* Ethernet PHY interrupt */
+			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x000b1
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX	0x1b0b0
+			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX	0x1b0b0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
+			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
+		>;
+	};
+
+	pinctrl_gpio_bl_on: gpioblon {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
+		>;
+	};
+
+	pinctrl_gpio_keys: gpio1io04grp {
+		fsl,pins = <
+			/* Power button */
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+		>;
+	};
+
+	pinctrl_hdmi_cec: hdmicecgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+		>;
+	};
+
+	pinctrl_hdmi_ddc: hdmiddcgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL	0x4001b8b1
+			MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA	0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__I2C3_SCL	0x4001b8b1
+			MX6QDL_PAD_EIM_D18__I2C3_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3_recovery: i2c3recoverygrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__GPIO3_IO17	0x4001b8b1
+			MX6QDL_PAD_EIM_D18__GPIO3_IO18	0x4001b8b1
+		>;
+	};
+
+	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0x61
+			/* DE */
+			MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15	0x61
+			/* HSync */
+			MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02	0x61
+			/* VSync */
+			MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03	0x61
+			MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0x61
+			MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01	0x61
+			MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02	0x61
+			MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03	0x61
+			MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04	0x61
+			MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05	0x61
+			MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06	0x61
+			MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07	0x61
+			MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08	0x61
+			MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09	0x61
+			MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10	0x61
+			MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11	0x61
+			MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12	0x61
+			MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13	0x61
+			MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14	0x61
+			MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15	0x61
+			MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16	0x61
+			MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17	0x61
+			MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18	0x61
+			MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19	0x61
+			MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20	0x61
+			MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21	0x61
+			MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22	0x61
+			MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23	0x61
+		>;
+	};
+
+	pinctrl_ipu2_vdac: ipu2vdacgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK	0xd1
+			MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15		0xd1
+			MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02		0xd1
+			MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03		0xd1
+			MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00	0xf9
+			MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01	0xf9
+			MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02	0xf9
+			MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03	0xf9
+			MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04	0xf9
+			MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05	0xf9
+			MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06	0xf9
+			MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07	0xf9
+			MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08	0xf9
+			MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09	0xf9
+			MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10	0xf9
+			MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11	0xf9
+			MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12	0xf9
+			MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13	0xf9
+			MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14	0xf9
+			MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15	0xf9
+		>;
+	};
+
+	pinctrl_mmc_cd: gpiommccdgrp {
+		fsl,pins = <
+			 /* MMC1 CD */
+			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20	0x000b0
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__PWM1_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__PWM2_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT1__PWM3_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT2__PWM4_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+		fsl,pins = <
+			/* USBH_EN */
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00	0x0f058
+		>;
+	};
+
+	pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
+		fsl,pins = <
+			/* USBH_HUB_EN */
+			MX6QDL_PAD_EIM_D28__GPIO3_IO28	0x0f058
+		>;
+	};
+
+	pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
+		fsl,pins = <
+			/* USBO1 power en */
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22	0x0f058
+		>;
+	};
+
+	pinctrl_reset_moci: gpioresetmocigrp {
+		fsl,pins = <
+			/* RESET_MOCI control */
+			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x0f058
+		>;
+	};
+
+	pinctrl_sd_cd: gpiosdcdgrp {
+		fsl,pins = <
+			/* SD1 CD */
+			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x000b0
+		>;
+	};
+
+	pinctrl_spdif: spdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_16__SPDIF_IN	0x1b0b0
+			MX6QDL_PAD_GPIO_17__SPDIF_OUT	0x1b0b0
+		>;
+	};
+
+	pinctrl_touch_int: gpiotouchintgrp {
+		fsl,pins = <
+			/* STMPE811 interrupt */
+			MX6QDL_PAD_KEY_COL2__GPIO4_IO10	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart1_dce: uart1dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart1_dte: uart1dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D19__UART1_RTS_B		0x1b0b1
+			MX6QDL_PAD_EIM_D20__UART1_CTS_B		0x1b0b1
+		>;
+	};
+
+	/* Additional DTR, DSR, DCD */
+	pinctrl_uart1_ctrl: uart1ctrlgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__UART1_DCD_B	0x1b0b0
+			MX6QDL_PAD_EIM_D24__UART1_DTR_B	0x1b0b0
+			MX6QDL_PAD_EIM_D25__UART1_DSR_B	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart2_dce: uart2dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart2_dte: uart2dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT6__UART2_RTS_B	0x1b0b1
+			MX6QDL_PAD_SD4_DAT5__UART2_CTS_B	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart4_dce: uart4dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart4_dte: uart4dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_RX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart5_dce: uart5dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart5_dte: uart5dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__UART5_RX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
+		>;
+	};
+
+	pinctrl_usdhc1_4bit: usdhc1grp_4bit {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17071
+		>;
+	};
+
+	pinctrl_usdhc1_8bit: usdhc1grp_8bit {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D0__SD1_DATA4	0x17071
+			MX6QDL_PAD_NANDF_D1__SD1_DATA5	0x17071
+			MX6QDL_PAD_NANDF_D2__SD1_DATA6	0x17071
+			MX6QDL_PAD_NANDF_D3__SD1_DATA7	0x17071
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD	0x17071
+			MX6QDL_PAD_SD2_CLK__SD2_CLK	0x10071
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0	0x17071
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1	0x17071
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2	0x17071
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3	0x17071
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+			/* eMMC reset */
+			MX6QDL_PAD_SD3_RST__SD3_RESET	0x17059
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx6-colibri.dts b/arch/arm/dts/imx6-colibri.dts
new file mode 100644
index 0000000..5c9f1f0
--- /dev/null
+++ b/arch/arm/dts/imx6-colibri.dts
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6dl.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX6DL/S";
+	compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
+
+	/* Will be filled by the bootloader */
+	memory@10000000 {
+		device_type = "memory";
+		reg = <0x10000000 0>;
+	};
+
+	aliases {
+		mmc0 = &usdhc3;
+		mmc1 = &usdhc1;
+		usb0 = &usbotg; /* required for ums */
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	reg_module_3v3: regulator-module-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_host_vbus: regulator-usb-host-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
+		regulator-name = "usb_host_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* USBH_PEN */
+	};
+};
+
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* vgen1: unused */
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* vgen3: unused */
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+/*
+ * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_recovery>;
+	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+/* Colibri UART_A */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
+	fsl,dte-mode;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Colibri UART_B */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_dte>;
+	fsl,dte-mode;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+/* Colibri UART_C */
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_dte>;
+	fsl,dte-mode;
+	status = "okay";
+};
+
+/* Colibri USBH */
+&usbh1 {
+	dr_mode = "host";
+	vbus-supply = <&reg_usb_host_vbus>;
+	status = "okay";
+};
+
+/* Colibri USBC */
+&usbotg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
+	cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
+	disable-wp;
+	vqmmc-supply = <&reg_module_3v3>;
+	bus-width = <4>;
+	no-1-8-v;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	vqmmc-supply = <&reg_module_3v3>;
+	bus-width = <8>;
+	no-1-8-v;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_ecspi4: ecspi4grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D22__ECSPI4_MISO	0x100b1
+			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI	0x100b1
+			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK	0x100b1
+			/* SPI CS */
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02	0x000b1
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK     ((1<<30) | 0x1b0b0)
+		>;
+	};
+
+	pinctrl_gpio_bl_on: gpioblon {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26	0x1b0b0
+		>;
+	};
+
+	pinctrl_hdmi_ddc: hdmiddcgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL	0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
+			MX6QDL_PAD_EIM_D16__I2C2_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL	0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3_recovery: i2c3recoverygrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__GPIO1_IO03	0x4001b8b1
+			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x4001b8b1
+		>;
+	};
+
+	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0xa1
+			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0xa1
+			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0xa1
+			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0xa1
+			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0xa1
+			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0xa1
+			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0xa1
+			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0xa1
+			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0xa1
+			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0xa1
+			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0xa1
+			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0xa1
+			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0xa1
+			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0xa1
+			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0xa1
+			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0xa1
+			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0xa1
+			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0xa1
+			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0xa1
+			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0xa1
+			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0xa1
+			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0xa1
+		>;
+	};
+
+	pinctrl_mmc_cd: gpiommccd {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D5__GPIO2_IO05	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__PWM1_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__PWM2_OUT	0x1b0b1
+			MX6QDL_PAD_EIM_A21__GPIO2_IO17	0x00040
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT1__PWM3_OUT	0x1b0b1
+			MX6QDL_PAD_EIM_A22__GPIO2_IO16	0x00040
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT2__PWM4_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+		fsl,pins = <
+			/* SODIMM 129 USBH_PEN */
+			MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x0f058
+		>;
+	};
+
+	pinctrl_uart1_dce: uart1dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart1_dte: uart1dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D19__UART1_RTS_B		0x1b0b1
+			MX6QDL_PAD_EIM_D20__UART1_CTS_B		0x1b0b1
+		>;
+	};
+
+	/* Additional DTR, DSR, DCD */
+	pinctrl_uart1_ctrl: uart1ctrlgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__UART1_DCD_B	0x1b0b0
+			MX6QDL_PAD_EIM_D24__UART1_DTR_B	0x1b0b0
+			MX6QDL_PAD_EIM_D25__UART1_DSR_B	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart2_dte: uart2dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT6__UART2_RTS_B	0x1b0b1
+			MX6QDL_PAD_SD4_DAT5__UART2_CTS_B	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart3_dte: uart3dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CLK__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_CMD__UART3_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17071
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+			/* eMMC reset */
+			MX6QDL_PAD_SD3_RST__SD3_RESET	0x17059
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx6dl-wandboard-revb1.dts b/arch/arm/dts/imx6dl-wandboard-revb1.dts
new file mode 100644
index 0000000..738db4f
--- /dev/null
+++ b/arch/arm/dts/imx6dl-wandboard-revb1.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-wandboard-revb1.dtsi"
+
+/ {
+	model = "Wandboard i.MX6 Dual Lite Board rev B1";
+	compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
+
+	memory@10000000 {
+		reg = <0x10000000 0x40000000>;
+	};
+};
diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts
new file mode 100644
index 0000000..deaec63
--- /dev/null
+++ b/arch/arm/dts/imx6q-bx50v3.dts
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR X11 */
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2018 General Electric Company
+ * Based on imx6q-ba16.dtsi and imx6q-bx50v3.dtsi from kernel 4.20.5.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "General Electric Bx50v3";
+	compatible = "ge,imx6q-bx50v3", "advantech,imx6q-ba16", "fsl,imx6q";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO	0x100b1
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI	0x100b1
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK	0x100b1
+			/* SPI1 CS */
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30	0x1b0b0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+		>;
+	};
+
+	pinctrl_usdhc3_reset: usdhc3grp-reset {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_RST__SD3_RESET   0x170F9
+		>;
+	};
+};
+
+&usdhc1 {
+	status = "disabled";
+};
+
+&usdhc2 {
+	status = "disabled";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
+	bus-width = <8>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&usdhc4 {
+	status = "disabled";
+};
+
+/* SPI NOR */
+&ecspi1 {
+	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+
+	flash: n25q032@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/dts/imx6q-tbs2910.dts b/arch/arm/dts/imx6q-tbs2910.dts
new file mode 100644
index 0000000..21e62c0
--- /dev/null
+++ b/arch/arm/dts/imx6q-tbs2910.dts
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2014-2019 Soeren Moch <smoch@web.de>
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "TBS2910 Matrix ARM mini PC";
+	compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	aliases {
+		mmc0 = &usdhc2;
+		mmc1 = &usdhc3;
+		mmc2 = &usdhc4;
+		usb0 = &usbotg;
+	};
+
+	memory@10000000 {
+		reg = <0x10000000 0x80000000>;
+	};
+
+	fan {
+		compatible = "gpio-fan";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_fan>;
+		gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <0    0
+				      3000 1>;
+	};
+
+	ir_recv {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ir>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		blue {
+			label = "blue_status_led";
+			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+			default-state = "keep";
+		};
+	};
+
+	reg_2p5v: regulator-2p5v {
+		compatible = "regulator-fixed";
+		regulator-name = "2P5V";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_5p0v: regulator-5p0v {
+		compatible = "regulator-fixed";
+		regulator-name = "5P0V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	sound-sgtl5000 {
+		audio-codec = <&sgtl5000>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "On-board Codec";
+		mux-ext-port = <3>;
+		mux-int-port = <1>;
+		ssi-controller = <&ssi1>;
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "On-board SPDIF";
+		spdif-controller = <&spdif>;
+		spdif-out;
+	};
+};
+
+&audmux {
+	status = "okay";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&hdmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	sgtl5000: sgtl5000@a {
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		compatible = "fsl,sgtl5000";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sgtl5000>;
+		reg = <0x0a>;
+		VDDA-supply = <&reg_2p5v>;
+		VDDIO-supply = <&reg_3p3v>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	rtc: ds1307@68 {
+		compatible = "dallas,ds1307";
+		reg = <0x68>;
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&sata {
+	fsl,transmit-level-mV = <1104>;
+	fsl,transmit-boost-mdB = <3330>;
+	fsl,transmit-atten-16ths = <16>;
+	fsl,receive-eq-mdB = <3000>;
+	status = "okay";
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	status = "okay";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_5p0v>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_5p0v>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <8>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
+	non-removable;
+	no-1-8-v;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
+		>;
+	};
+
+	pinctrl_gpio_fan: gpiofangrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
+		>;
+	};
+
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
+		>;
+	};
+
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
+		>;
+	};
+
+	pinctrl_ir: irgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
+		>;
+	};
+
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
+		>;
+	};
+
+	pinctrl_sgtl5000: sgtl5000grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
+			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
+			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
+			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
+			MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
+		>;
+	};
+
+	pinctrl_spdif: spdifgrp {
+		fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
+			MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
+			MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
+			MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
+			MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
+		>;
+	};
+
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
+			MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
new file mode 100644
index 0000000..855dc6f
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "imx6qdl-wandboard.dtsi"
+
+&iomuxc {
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx6qdl-wandboard {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000	/* uSDHC1 CD */
+				MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x80000000	/* uSDHC3 CD */
+				MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x0f0b0		/* WL_REF_ON */
+				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x0f0b0		/* WL_RST_N */
+				MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x000b0		/* WL_REG_ON */
+				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x80000000	/* WL_HOST_WAKE */
+				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x80000000	/* WL_WAKE */
+				MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x80000000	/* RGMII_nRST */
+				MX6QDL_PAD_EIM_DA13__GPIO3_IO13		0x80000000	/* BT_ON */
+				MX6QDL_PAD_EIM_DA14__GPIO3_IO14		0x80000000	/* BT_WAKE */
+				MX6QDL_PAD_EIM_DA15__GPIO3_IO15		0x80000000	/* BT_HOST_WAKE */
+			>;
+		};
+	};
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-wandboard.dtsi b/arch/arm/dts/imx6qdl-wandboard.dtsi
new file mode 100644
index 0000000..4d03d49
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-wandboard.dtsi
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	sound {
+		compatible = "fsl,imx6-wandboard-sgtl5000",
+			     "fsl,imx-audio-sgtl5000";
+		model = "imx6-wandboard-sgtl5000";
+		ssi-controller = <&ssi1>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+		mux-int-port = <1>;
+		mux-ext-port = <3>;
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-out;
+	};
+
+	reg_2p5v: regulator-2p5v {
+		compatible = "regulator-fixed";
+		regulator-name = "2P5V";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_otg_vbus: regulator-usbotgvbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotgvbus>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c1>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	codec: sgtl5000@a {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mclk>;
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		VDDA-supply = <&reg_2p5v>;
+		VDDIO-supply = <&reg_3p3v>;
+		lrclk-strength = <3>;
+	};
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx6qdl-wandboard {
+
+		pinctrl_audmux: audmuxgrp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
+				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
+				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
+				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+			>;
+		};
+
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
+				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_mclk: mclkgrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+				MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
+				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
+			>;
+		};
+
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
+			>;
+		};
+
+		pinctrl_usbotgvbus: usbotgvbusgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
+				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
+				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
+				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
+				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
+				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+			>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+	fsl,err006687-workaround-present;
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	status = "okay";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbh1 {
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index e4daf15..c0a9478 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -145,6 +145,7 @@
 		compatible = "simple-bus";
 		interrupt-parent = <&gpc>;
 		ranges;
+		u-boot,dm-pre-reloc;
 
 		dma_apbh: dma-apbh@110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -1261,6 +1262,7 @@
 				 <&clks IMX6QDL_CLK_IPU1_DI1>;
 			clock-names = "bus", "di0", "di1";
 			resets = <&src 2>;
+			u-boot,dm-pre-reloc;
 
 			ipu1_csi0: port@0 {
 				reg = <0>;
diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
new file mode 100644
index 0000000..322c858
--- /dev/null
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (c) 2019 Simon Goldschmidt
+ */
+/{
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 2458d67..51a6a51 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -84,6 +84,7 @@
 				#dma-requests = <32>;
 				clocks = <&l4_main_clk>;
 				clock-names = "apb_pclk";
+				resets = <&rst DMA_RESET>;
 			};
 		};
 
@@ -100,6 +101,7 @@
 			reg = <0xffc00000 0x1000>;
 			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
 			clocks = <&can0_clk>;
+			resets = <&rst CAN0_RESET>;
 			status = "disabled";
 		};
 
@@ -108,6 +110,7 @@
 			reg = <0xffc01000 0x1000>;
 			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
 			clocks = <&can1_clk>;
+			resets = <&rst CAN1_RESET>;
 			status = "disabled";
 		};
 
@@ -585,6 +588,7 @@
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xff708000 0x1000>;
 			clocks = <&l4_mp_clk>;
+			resets = <&rst GPIO0_RESET>;
 			status = "disabled";
 
 			porta: gpio-controller@0 {
@@ -605,6 +609,7 @@
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xff709000 0x1000>;
 			clocks = <&l4_mp_clk>;
+			resets = <&rst GPIO1_RESET>;
 			status = "disabled";
 
 			portb: gpio-controller@0 {
@@ -625,6 +630,7 @@
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xff70a000 0x1000>;
 			clocks = <&l4_mp_clk>;
+			resets = <&rst GPIO2_RESET>;
 			status = "disabled";
 
 			portc: gpio-controller@0 {
@@ -735,6 +741,7 @@
 			#size-cells = <0>;
 			clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
 			clock-names = "biu", "ciu";
+			resets = <&rst SDMMC_RESET>;
 			status = "disabled";
 		};
 
@@ -746,9 +753,9 @@
 			      <0xffb80000 0x10000>;
 			reg-names = "nand_data", "denali_reg";
 			interrupts = <0x0 0x90 0x4>;
-			dma-mask = <0xffffffff>;
 			clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 			clock-names = "nand", "nand_x", "ecc";
+			resets = <&rst NAND_RESET>;
 			status = "disabled";
 		};
 
@@ -759,7 +766,7 @@
 
 		qspi: spi@ff705000 {
 			compatible = "cdns,qspi-nor";
-                        #address-cells = <1>;
+			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xff705000 0x1000>,
 			      <0xffa00000 0x1000>;
@@ -768,6 +775,7 @@
 			cdns,fifo-width = <4>;
 			cdns,trigger-address = <0x00000000>;
 			clocks = <&qspi_clk>;
+			resets = <&rst QSPI_RESET>;
 			status = "disabled";
 		};
 
@@ -783,9 +791,10 @@
 			reg = <0xfffec000 0x100>;
 		};
 
-		sdr: sdr@ffc25000 {
+		sdr: sdr@ffc20000 {
 			compatible = "altr,sdr-ctl", "syscon";
-			reg = <0xffc25000 0x1000>;
+			reg = <0xffc20000 0x6000>;
+			resets = <&rst SDR_RESET>;
 		};
 
 		sdramedac {
@@ -802,6 +811,7 @@
 			interrupts = <0 154 4>;
 			num-cs = <4>;
 			clocks = <&spi_m_clk>;
+			resets = <&rst SPIM0_RESET>;
 			status = "disabled";
 		};
 
@@ -813,6 +823,7 @@
 			interrupts = <0 155 4>;
 			num-cs = <4>;
 			clocks = <&spi_m_clk>;
+			resets = <&rst SPIM1_RESET>;
 			status = "disabled";
 		};
 
@@ -879,6 +890,7 @@
 			dmas = <&pdma 28>,
 			       <&pdma 29>;
 			dma-names = "tx", "rx";
+			resets = <&rst UART0_RESET>;
 		};
 
 		uart1: serial1@ffc03000 {
@@ -891,6 +903,7 @@
 			dmas = <&pdma 30>,
 			       <&pdma 31>;
 			dma-names = "tx", "rx";
+			resets = <&rst UART1_RESET>;
 		};
 
 		usbphy0: usbphy {
@@ -930,6 +943,7 @@
 			reg = <0xffd02000 0x1000>;
 			interrupts = <0 171 4>;
 			clocks = <&osc1>;
+			resets = <&rst L4WD0_RESET>;
 			status = "disabled";
 		};
 
@@ -938,6 +952,7 @@
 			reg = <0xffd03000 0x1000>;
 			interrupts = <0 172 4>;
 			clocks = <&osc1>;
+			resets = <&rst L4WD1_RESET>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
index e75f290..dfaff4c 100644
--- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
 	aliases {
 		spi0 = "/soc/spi@ff705000";
 		udc0 = &usb1;
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &watchdog0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index a387071..6439daa 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
 	model = "Devboards.de DBM-SoC1";
@@ -24,10 +25,6 @@
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
index 08d81da..0219c69 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
@@ -6,14 +6,12 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
 	aliases {
 		udc0 = &usb1;
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &watchdog0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index e910574..b620dd8 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -6,6 +6,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
 	model = "Terasic DE10-Nano";
@@ -26,10 +27,6 @@
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index 4f076bc..ff1e61e 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
 	model = "Terasic DE1-SoC";
@@ -24,10 +25,6 @@
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 93e4d45..2d31412 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
 	model = "SoCFPGA Cyclone V IS1";
@@ -31,10 +32,6 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
index 2fafd7e..7d9874c 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
 	aliases {
 		spi0 = "/soc/spi@ff705000";
 		udc0 = &usb1;
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &can0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
index 7ef3053..85cc396 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
 	aliases {
 		spi0 = "/soc/spi@ff705000";
 		udc0 = &usb1;
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &watchdog0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
index 1003115..0a4d54e 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
 	aliases {
 		spi0 = "/soc/spi@ff705000";
 		udc0 = &usb1;
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &watchdog0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 93c3fa4..8d5d399 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -76,7 +76,6 @@
 
 &qspi {
 	status = "okay";
-	u-boot,dm-pre-reloc;
 
 	flash: flash@0 {
 		#address-cells = <1>;
@@ -91,6 +90,5 @@
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
 		status = "okay";
-		u-boot,dm-pre-reloc;
 	};
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 1a18c4f..bb29da6 100644
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
 	model = "SoCFPGA Cyclone V SR1500";
@@ -27,10 +28,6 @@
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
index e05ca82..db55a4e 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
 	aliases {
 		spi0 = "/soc/spi@ff705000";
 		udc0 = &usb0;
 	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
 };
 
 &watchdog0 {
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
old mode 100644
new mode 100755
index ee93725..d1ae2fa
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -237,6 +237,19 @@
 			reg = <0xffe00000 0x100000>;
 		};
 
+		qspi: spi@ff8d2000 {
+			compatible = "cdns,qspi-nor";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xff8d2000 0x100>,
+			      <0xff900000 0x100000>;
+			interrupts = <0 3 4>;
+			cdns,fifo-depth = <128>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x00000000>;
+			status = "disabled";
+		};
+
 		rst: rstmgr@ffd11000 {
 			#reset-cells = <1>;
 			compatible = "altr,rst-mgr";
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
new file mode 100755
index 0000000..e1cfb52
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+/{
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&flash0 {
+	compatible = "jedec,spi-nor";
+	spi-max-frequency = <100000000>;
+	spi-tx-bus-width = <4>;
+	spi-rx-bus-width = <4>;
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
old mode 100644
new mode 100755
index 6e8ddcd..2745050
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -36,7 +36,9 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0 0 0 0x80000000>; /* 2GB */
+		/* 4GB */
+		reg = <0 0x00000000 0 0x80000000>,
+		      <1 0x80000000 0 0x80000000>;
 		u-boot,dm-pre-reloc;
 	};
 };
@@ -85,6 +87,41 @@
 	smplsel = <0>;
 };
 
+&qspi {
+	flash0: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00a";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+
+		m25p,fast-read;
+		cdns,page-size = <256>;
+		cdns,block-size = <16>;
+		cdns,read-delay = <1>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x4000000>;
+			};
+
+			qspi_rootfs: partition@4000000 {
+				label = "Root Filesystem - JFFS2";
+				reg = <0x4000000 0x4000000>;
+			};
+		};
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index c069875..0aae69b 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -375,6 +375,13 @@
 				};
 			};
 
+			stusb1600_pins_a: stusb1600-0 {
+				pins {
+					pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
+					bias-pull-up;
+				};
+			};
+
 			uart4_pins_a: uart4-0 {
 				pins1 {
 					pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index af7acfa..0f32a38 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -11,6 +11,7 @@
 	aliases {
 		i2c3 = &i2c4;
 		mmc0 = &sdmmc1;
+		usb0 = &usbotg_hs;
 	};
 	config {
 		u-boot,boot-led = "heartbeat";
@@ -190,7 +191,7 @@
 };
 
 &usbotg_hs {
-	usb1600;
+	u-boot,force-b-session-valid;
 	hnp-srp-disable;
 };
 
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 0882765..e36773d 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -67,6 +67,24 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 
+	typec: stusb1600@28 {
+		compatible = "st,stusb1600";
+		reg = <0x28>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-parent = <&gpioi>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&stusb1600_pins_a>;
+
+		status = "okay";
+
+		typec_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "sink";
+			power-opmode = "default";
+		};
+	};
+
 	pmic: stpmic@33 {
 		compatible = "st,stpmic1";
 		reg = <0x33>;
@@ -249,11 +267,25 @@
 	status = "okay";
 };
 
-&usbphyc {
-	vdd3v3-supply = <&vdd_usb>;
+&usbotg_hs {
+	dr_mode = "peripheral";
+	phys = <&usbphyc_port1 0>;
+	phy-names = "usb2-phy";
 	status = "okay";
 };
 
+&usbphyc {
+	status = "okay";
+};
+
+&usbphyc_port0 {
+	phy-supply = <&vdd_usb>;
+};
+
+&usbphyc_port1 {
+	phy-supply = <&vdd_usb>;
+};
+
 &vrefbuf {
 	regulator-min-microvolt = <2500000>;
 	regulator-max-microvolt = <2500000>;
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 2664c9c..0366782 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -382,18 +382,10 @@
 	status = "okay";
 };
 
-&usbotg_hs {
-	usb33d-supply = <&usb33>;
-};
-
 &usbphyc_port0 {
 	phy-supply = <&vdd_usb>;
-	vdda1v1-supply = <&reg11>;
-	vdda1v8-supply = <&reg18>;
 };
 
 &usbphyc_port1 {
 	phy-supply = <&vdd_usb>;
-	vdda1v1-supply = <&reg11>;
-	vdda1v8-supply = <&reg18>;
 };
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 8b92b1f..5b19e44 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -12,6 +12,7 @@
 		i2c4 = &i2c5;
 		pinctrl2 = &stmfx_pinctrl;
 		spi0 = &qspi;
+		usb0 = &usbotg_hs;
 	};
 };
 
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 7eb4bee..9463433 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -825,7 +825,7 @@
 		};
 
 		usbotg_hs: usb-otg@49000000 {
-			compatible = "snps,dwc2";
+			compatible = "st,stm32mp1-hsotg", "snps,dwc2";
 			reg = <0x49000000 0x10000>;
 			clocks = <&rcc USBO_K>;
 			clock-names = "otg";
@@ -836,6 +836,7 @@
 			g-np-tx-fifo-size = <32>;
 			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 			dr_mode = "otg";
+			usb33d-supply = <&usb33>;
 			status = "disabled";
 		};
 
@@ -1161,6 +1162,8 @@
 			reg = <0x5a006000 0x1000>;
 			clocks = <&rcc USBPHY_K>;
 			resets = <&rcc USBPHY_R>;
+			vdda1v1-supply = <&reg11>;
+			vdda1v8-supply = <&reg18>;
 			status = "disabled";
 
 			usbphyc_port0: usb-phy@0 {
diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi
index 0612c19..62e2794 100644
--- a/arch/arm/dts/sun50i-h6-orangepi.dtsi
+++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi
@@ -21,17 +21,55 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		power {
+			label = "orangepi:red:power";
+			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+			default-state = "on";
+		};
+
+		status {
+			label = "orangepi:green:status";
+			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+		};
+	};
+
+	reg_vcc5v: vcc5v {
+		/* board wide 5V supply directly from the DC jack */
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci3 {
+	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>;
 	vmmc-supply = <&reg_cldo1>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
 	bus-width = <4>;
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
+&ohci3 {
+	status = "okay";
+};
+
 &r_i2c {
 	status = "okay";
 
@@ -43,6 +81,14 @@
 		interrupt-controller;
 		#interrupt-cells = <1>;
 		x-powers,self-working-mode;
+		vina-supply = <&reg_vcc5v>;
+		vinb-supply = <&reg_vcc5v>;
+		vinc-supply = <&reg_vcc5v>;
+		vind-supply = <&reg_vcc5v>;
+		vine-supply = <&reg_vcc5v>;
+		aldoin-supply = <&reg_vcc5v>;
+		bldoin-supply = <&reg_vcc5v>;
+		cldoin-supply = <&reg_vcc5v>;
 
 		regulators {
 			reg_aldo1: aldo1 {
@@ -148,3 +194,15 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usb2otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2phy {
+	usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */
+	usb0_vbus-supply = <&reg_vcc5v>;
+	usb3_vbus-supply = <&reg_vcc5v>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts
index ceffc40..4802902 100644
--- a/arch/arm/dts/sun50i-h6-pine-h64.dts
+++ b/arch/arm/dts/sun50i-h6-pine-h64.dts
@@ -14,6 +14,7 @@
 	compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
 
 	aliases {
+		ethernet0 = &emac;
 		serial0 = &uart0;
 	};
 
@@ -21,6 +22,17 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -39,23 +51,79 @@
 			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
 		};
 	};
+
+	reg_usb_vbus: vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		startup-delay-us = <100000>;
+		gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ext_rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-handle = <&ext_rgmii_phy>;
+	phy-supply = <&reg_aldo2>;
+	allwinner,rx-delay-ps = <200>;
+	allwinner,tx-delay-ps = <200>;
+	status = "okay";
+};
+
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&de {
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci3 {
+	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>;
 	vmmc-supply = <&reg_cldo1>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
 	status = "okay";
 };
 
 &mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins>;
 	vmmc-supply = <&reg_cldo1>;
 	vqmmc-supply = <&reg_bldo2>;
 	non-removable;
 	cap-mmc-hw-reset;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci3 {
 	status = "okay";
 };
 
@@ -83,6 +151,7 @@
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
 				regulator-name = "vcc-ac200";
+				regulator-enable-ramp-delay = <100000>;
 			};
 
 			reg_aldo3: aldo3 {
@@ -183,3 +252,14 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usb2otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2phy {
+	usb0_vbus-supply = <&reg_usb_vbus>;
+	usb3_vbus-supply = <&reg_usb_vbus>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
index cfa5fff..e0dc4a0 100644
--- a/arch/arm/dts/sun50i-h6.dtsi
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -6,8 +6,11 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/sun50i-h6-ccu.h>
 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
 #include <dt-bindings/reset/sun50i-h6-ccu.h>
 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -19,34 +22,40 @@
 		#size-cells = <0>;
 
 		cpu0: cpu@0 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0>;
 			enable-method = "psci";
 		};
 
 		cpu1: cpu@1 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <1>;
 			enable-method = "psci";
 		};
 
 		cpu2: cpu@2 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <2>;
 			enable-method = "psci";
 		};
 
 		cpu3: cpu@3 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <3>;
 			enable-method = "psci";
 		};
 	};
 
+	de: display-engine {
+		compatible = "allwinner,sun50i-h6-display-engine";
+		allwinner,pipelines = <&mixer0>;
+		status = "disabled";
+	};
+
 	iosc: internal-osc-clk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -92,6 +101,99 @@
 		#size-cells = <1>;
 		ranges;
 
+		display-engine@1000000 {
+			compatible = "allwinner,sun50i-h6-de3",
+				     "allwinner,sun50i-a64-de2";
+			reg = <0x1000000 0x400000>;
+			allwinner,sram = <&de2_sram 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x1000000 0x400000>;
+
+			display_clocks: clock@0 {
+				compatible = "allwinner,sun50i-h6-de3-clk";
+				reg = <0x0 0x10000>;
+				clocks = <&ccu CLK_DE>,
+					 <&ccu CLK_BUS_DE>;
+				clock-names = "mod",
+					      "bus";
+				resets = <&ccu RST_BUS_DE>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+
+			mixer0: mixer@100000 {
+				compatible = "allwinner,sun50i-h6-de3-mixer-0";
+				reg = <0x100000 0x100000>;
+				clocks = <&display_clocks CLK_BUS_MIXER0>,
+					 <&display_clocks CLK_MIXER0>;
+				clock-names = "bus",
+					      "mod";
+				resets = <&display_clocks RST_MIXER0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					mixer0_out: port@1 {
+						reg = <1>;
+
+						mixer0_out_tcon_top_mixer0: endpoint {
+							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+						};
+					};
+				};
+			};
+		};
+
+		video-codec@1c0e000 {
+			compatible = "allwinner,sun50i-h6-video-engine";
+			reg = <0x01c0e000 0x2000>;
+			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+				 <&ccu CLK_MBUS_VE>;
+			clock-names = "ahb", "mod", "ram";
+			resets = <&ccu RST_BUS_VE>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			allwinner,sram = <&ve_sram 1>;
+		};
+
+		syscon: syscon@3000000 {
+			compatible = "allwinner,sun50i-h6-system-control",
+				     "allwinner,sun50i-a64-system-control";
+			reg = <0x03000000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_c: sram@28000 {
+				compatible = "mmio-sram";
+				reg = <0x00028000 0x1e000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00028000 0x1e000>;
+
+				de2_sram: sram-section@0 {
+					compatible = "allwinner,sun50i-h6-sram-c",
+						     "allwinner,sun50i-a64-sram-c";
+					reg = <0x0000 0x1e000>;
+				};
+			};
+
+			sram_c1: sram@1a00000 {
+				compatible = "mmio-sram";
+				reg = <0x01a00000 0x200000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x01a00000 0x200000>;
+
+				ve_sram: sram-section@0 {
+					compatible = "allwinner,sun50i-h6-sram-c1",
+						     "allwinner,sun4i-a10-sram-c1";
+					reg = <0x000000 0x200000>;
+				};
+			};
+		};
+
 		ccu: clock@3001000 {
 			compatible = "allwinner,sun50i-h6-ccu";
 			reg = <0x03001000 0x1000>;
@@ -101,15 +203,9 @@
 			#reset-cells = <1>;
 		};
 
-		gic: interrupt-controller@3021000 {
-			compatible = "arm,gic-400";
-			reg = <0x03021000 0x1000>,
-			      <0x03022000 0x2000>,
-			      <0x03024000 0x2000>,
-			      <0x03026000 0x2000>;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
+		sid: sid@3006000 {
+			compatible = "allwinner,sun50i-h6-sid";
+			reg = <0x03006000 0x400>;
 		};
 
 		pio: pinctrl@300b000 {
@@ -126,6 +222,19 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			ext_rgmii_pins: rgmii-pins {
+				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+				       "PD5", "PD7", "PD8", "PD9", "PD10",
+				       "PD11", "PD12", "PD13", "PD19", "PD20";
+				function = "emac";
+				drive-strength = <40>;
+			};
+
+			hdmi_pins: hdmi-pins {
+				pins = "PH8", "PH9", "PH10";
+				function = "hdmi";
+			};
+
 			mmc0_pins: mmc0-pins {
 				pins = "PF0", "PF1", "PF2", "PF3",
 				       "PF4", "PF5";
@@ -143,12 +252,23 @@
 				bias-pull-up;
 			};
 
-			uart0_ph_pins: uart0-ph {
+			uart0_ph_pins: uart0-ph-pins {
 				pins = "PH0", "PH1";
 				function = "uart0";
 			};
 		};
 
+		gic: interrupt-controller@3021000 {
+			compatible = "arm,gic-400";
+			reg = <0x03021000 0x1000>,
+			      <0x03022000 0x2000>,
+			      <0x03024000 0x2000>,
+			      <0x03026000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
 		mmc0: mmc@4020000 {
 			compatible = "allwinner,sun50i-h6-mmc",
 				     "allwinner,sun50i-a64-mmc";
@@ -158,6 +278,8 @@
 			resets = <&ccu RST_BUS_MMC0>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -186,6 +308,8 @@
 			resets = <&ccu RST_BUS_MMC2>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc2_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -235,6 +359,250 @@
 			status = "disabled";
 		};
 
+		emac: ethernet@5020000 {
+			compatible = "allwinner,sun50i-h6-emac",
+				     "allwinner,sun50i-a64-emac";
+			syscon = <&syscon>;
+			reg = <0x05020000 0x10000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			resets = <&ccu RST_BUS_EMAC>;
+			reset-names = "stmmaceth";
+			clocks = <&ccu CLK_BUS_EMAC>;
+			clock-names = "stmmaceth";
+			status = "disabled";
+
+			mdio: mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		usb2otg: usb@5100000 {
+			compatible = "allwinner,sun50i-h6-musb",
+				     "allwinner,sun8i-a33-musb";
+			reg = <0x05100000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usb2phy 0>;
+			phy-names = "usb";
+			extcon = <&usb2phy 0>;
+			status = "disabled";
+		};
+
+		usb2phy: phy@5100400 {
+			compatible = "allwinner,sun50i-h6-usb-phy";
+			reg = <0x05100400 0x24>,
+			      <0x05101800 0x4>,
+			      <0x05311800 0x4>;
+			reg-names = "phy_ctrl",
+				    "pmu0",
+				    "pmu3";
+			clocks = <&ccu CLK_USB_PHY0>,
+				 <&ccu CLK_USB_PHY3>;
+			clock-names = "usb0_phy",
+				      "usb3_phy";
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY3>;
+			reset-names = "usb0_reset",
+				      "usb3_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci0: usb@5101000 {
+			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
+			reg = <0x05101000 0x100>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_BUS_EHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>,
+				 <&ccu RST_BUS_EHCI0>;
+			status = "disabled";
+		};
+
+		ohci0: usb@5101400 {
+			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
+			reg = <0x05101400 0x100>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
+		ehci3: usb@5311000 {
+			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
+			reg = <0x05311000 0x100>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI3>,
+				 <&ccu CLK_BUS_EHCI3>,
+				 <&ccu CLK_USB_OHCI3>;
+			resets = <&ccu RST_BUS_OHCI3>,
+				 <&ccu RST_BUS_EHCI3>;
+			phys = <&usb2phy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci3: usb@5311400 {
+			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
+			reg = <0x05311400 0x100>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI3>,
+				 <&ccu CLK_USB_OHCI3>;
+			resets = <&ccu RST_BUS_OHCI3>;
+			phys = <&usb2phy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		hdmi: hdmi@6000000 {
+			compatible = "allwinner,sun50i-h6-dw-hdmi";
+			reg = <0x06000000 0x10000>;
+			reg-io-width = <1>;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+				 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
+				 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
+			clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
+				      "hdcp-bus";
+			resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
+			reset-names = "ctrl", "hdcp";
+			phys = <&hdmi_phy>;
+			phy-names = "hdmi-phy";
+			pinctrl-names = "default";
+			pinctrl-0 = <&hdmi_pins>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				hdmi_in: port@0 {
+					reg = <0>;
+
+					hdmi_in_tcon_top: endpoint {
+						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
+					};
+				};
+
+				hdmi_out: port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		hdmi_phy: hdmi-phy@6010000 {
+			compatible = "allwinner,sun50i-h6-hdmi-phy";
+			reg = <0x06010000 0x10000>;
+			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_HDMI>;
+			reset-names = "phy";
+			#phy-cells = <0>;
+		};
+
+		tcon_top: tcon-top@6510000 {
+			compatible = "allwinner,sun50i-h6-tcon-top";
+			reg = <0x06510000 0x1000>;
+			clocks = <&ccu CLK_BUS_TCON_TOP>,
+				 <&ccu CLK_TCON_TV0>;
+			clock-names = "bus",
+				      "tcon-tv0";
+			clock-output-names = "tcon-top-tv0";
+			resets = <&ccu RST_BUS_TCON_TOP>;
+			reset-names = "rst";
+			#clock-cells = <1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_top_mixer0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					tcon_top_mixer0_in_mixer0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+					};
+				};
+
+				tcon_top_mixer0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon_top_mixer0_out_tcon_tv: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
+					};
+				};
+
+				tcon_top_hdmi_in: port@4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <4>;
+
+					tcon_top_hdmi_in_tcon_tv: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_tv_out_tcon_top>;
+					};
+				};
+
+				tcon_top_hdmi_out: port@5 {
+					reg = <5>;
+
+					tcon_top_hdmi_out_hdmi: endpoint {
+						remote-endpoint = <&hdmi_in_tcon_top>;
+					};
+				};
+			};
+		};
+
+		tcon_tv: lcd-controller@6515000 {
+			compatible = "allwinner,sun50i-h6-tcon-tv",
+				     "allwinner,sun8i-r40-tcon-tv";
+			reg = <0x06515000 0x1000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_TCON_TV0>,
+				 <&tcon_top CLK_TCON_TOP_TV0>;
+			clock-names = "ahb",
+				      "tcon-ch1";
+			resets = <&ccu RST_BUS_TCON_TV0>;
+			reset-names = "lcd";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_tv_in: port@0 {
+					reg = <0>;
+
+					tcon_tv_in_tcon_top_mixer0: endpoint {
+						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
+					};
+				};
+
+				tcon_tv_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon_tv_out_tcon_top: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
+					};
+				};
+			};
+		};
+
 		r_ccu: clock@7010000 {
 			compatible = "allwinner,sun50i-h6-r-ccu";
 			reg = <0x07010000 0x400>;
@@ -266,7 +634,7 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
-			r_i2c_pins: r-i2c {
+			r_i2c_pins: r-i2c-pins {
 				pins = "PL0", "PL1";
 				function = "s_i2c";
 			};
diff --git a/arch/arm/dts/sun7i-a20-ainol-aw1.dts b/arch/arm/dts/sun7i-a20-ainol-aw1.dts
index 57fe006..5914c91 100644
--- a/arch/arm/dts/sun7i-a20-ainol-aw1.dts
+++ b/arch/arm/dts/sun7i-a20-ainol-aw1.dts
@@ -23,6 +23,6 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
index 763cb03..e2bfe00 100644
--- a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -73,8 +73,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_bpi_m1p>;
 
 		green {
 			label = "bananapi-m1-plus:green:usr";
@@ -90,15 +88,11 @@
 
 	mmc3_pwrseq: mmc3_pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		pinctrl-names = "default";
-		pinctrl-0 = <&mmc3_pwrseq_pin_bpi_m1p>;
 		reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */
 	};
 
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_power_pin_bpi_m1p>;
 		regulator-name = "gmac-3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -134,7 +128,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_gmac_3v3>;
@@ -156,8 +150,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -175,13 +167,11 @@
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
@@ -191,8 +181,6 @@
 &mmc3 {
 	#address-cells = <1>;
 	#size-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	mmc-pwrseq = <&mmc3_pwrseq>;
 	bus-width = <4>;
@@ -209,11 +197,6 @@
 	};
 };
 
-&mmc3_pins_a {
-	/* AP6210 requires pull-up */
-	bias-pull-up;
-};
-
 &ohci0 {
 	status = "okay";
 };
@@ -226,29 +209,6 @@
 	status = "okay";
 };
 
-&pio {
-	gmac_power_pin_bpi_m1p: gmac_power_pin@0 {
-		pins = "PH23";
-		function = "gpio_out";
-	};
-
-	led_pins_bpi_m1p: led_pins@0 {
-		pins = "PH24", "PH25";
-		function = "gpio_out";
-	};
-
-	mmc0_cd_pin_bpi_m1p: mmc0_cd_pin@0 {
-		pins = "PH10";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	mmc3_pwrseq_pin_bpi_m1p: mmc3_pwrseq_pin@0 {
-		pins = "PH22";
-		function = "gpio_out";
-	};
-};
-
 &reg_dcdc2 {
 	regulator-always-on;
 	regulator-min-microvolt = <1000000>;
@@ -280,7 +240,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-bananapi.dts b/arch/arm/dts/sun7i-a20-bananapi.dts
index 70dfc4a..81bc85d 100644
--- a/arch/arm/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/dts/sun7i-a20-bananapi.dts
@@ -76,8 +76,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_bananapi>;
 
 		green {
 			label = "bananapi:green:usr";
@@ -87,8 +85,6 @@
 
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_power_pin_bananapi>;
 		regulator-name = "gmac-3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -134,7 +130,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_gmac_3v3>;
@@ -156,8 +152,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -168,20 +162,16 @@
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
@@ -201,6 +191,11 @@
 };
 
 &pio {
+	vcc-pa-supply = <&reg_vcc3v3>;
+	vcc-pc-supply = <&reg_vcc3v3>;
+	vcc-pe-supply = <&reg_vcc3v3>;
+	vcc-pf-supply = <&reg_vcc3v3>;
+	vcc-pg-supply = <&reg_vcc3v3>;
 	gpio-line-names =
 		/* PA */
 		"ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3",
@@ -252,27 +247,11 @@
 		"IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
 		"", "", "", "", "", "", "", "";
 
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
 	};
-
-	mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
-		pins = "PH10";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	gmac_power_pin_bananapi: gmac_power_pin@0 {
-		pins = "PH23";
-		function = "gpio_out";
-	};
-
-	led_pins_bananapi: led_pins@0 {
-		pins = "PH24";
-		function = "gpio_out";
-	};
 };
 
 #include "axp209.dtsi"
@@ -316,27 +295,27 @@
 
 &spi0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_pins_a>,
-		    <&spi0_cs0_pins_a>,
-		    <&spi0_cs1_pins_a>;
+	pinctrl-0 = <&spi0_pi_pins>,
+		    <&spi0_cs0_pi_pin>,
+		    <&spi0_cs1_pi_pin>;
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
 &uart3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins_b>;
+	pinctrl-0 = <&uart3_ph_pins>;
 	status = "okay";
 };
 
 &uart7 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart7_pins_a>;
+	pinctrl-0 = <&uart7_pi_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-bananapro.dts b/arch/arm/dts/sun7i-a20-bananapro.dts
index 0898eb6..0176e9d 100644
--- a/arch/arm/dts/sun7i-a20-bananapro.dts
+++ b/arch/arm/dts/sun7i-a20-bananapro.dts
@@ -62,8 +62,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_bananapro>;
 
 		blue {
 			label = "bananapro:blue:usr";
@@ -78,15 +76,11 @@
 
 	wifi_pwrseq: wifi-pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		pinctrl-names = "default";
-		pinctrl-0 = <&vmmc3_pin_bananapro>;
 		reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>;
 	};
 
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_power_pin_bananapro>;
 		regulator-name = "gmac-3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -114,7 +108,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_gmac_3v3>;
@@ -126,8 +120,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -142,20 +134,16 @@
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
@@ -163,8 +151,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	mmc-pwrseq = <&wifi_pwrseq>;
 	bus-width = <4>;
@@ -188,74 +174,39 @@
 	status = "okay";
 };
 
-&pio {
-	gmac_power_pin_bananapro: gmac_power_pin@0 {
-		pins = "PH23";
-		function = "gpio_out";
-	};
-
-	led_pins_bananapro: led_pins@0 {
-		pins = "PH24", "PG2";
-		function = "gpio_out";
-	};
-
-	mmc0_cd_pin_bananapro: mmc0_cd_pin@0 {
-		pins = "PH10";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
-		pins = "PH0";
-		function = "gpio_out";
-	};
-
-	usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
-		pins = "PH1";
-		function = "gpio_out";
-	};
-
-	vmmc3_pin_bananapro: vmmc3_pin@0 {
-		pins = "PH22";
-		function = "gpio_out";
-	};
-};
-
 &reg_usb1_vbus {
-	pinctrl-0 = <&usb1_vbus_pin_bananapro>;
 	gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */
 	status = "okay";
 };
 
 &reg_usb2_vbus {
-	pinctrl-0 = <&usb2_vbus_pin_bananapro>;
 	gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
 	status = "okay";
 };
 
 &spi0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_pins_a>,
-		    <&spi0_cs0_pins_a>,
-		    <&spi0_cs1_pins_a>;
+	pinctrl-0 = <&spi0_pi_pins>,
+		    <&spi0_cs0_pi_pin>,
+		    <&spi0_cs1_pi_pin>;
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
 &uart4 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_b>;
+	pinctrl-0 = <&uart4_ph_pins>;
 	status = "okay";
 };
 
 &uart7 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart7_pins_a>;
+	pinctrl-0 = <&uart7_pi_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-cubieboard2.dts b/arch/arm/dts/sun7i-a20-cubieboard2.dts
index 942ac9d..200685b 100644
--- a/arch/arm/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/dts/sun7i-a20-cubieboard2.dts
@@ -74,8 +74,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_cubieboard2>;
 
 		blue {
 			label = "cubieboard2:blue:usr";
@@ -116,7 +114,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>;
+	pinctrl-0 = <&gmac_mii_pins>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	status = "okay";
@@ -137,8 +135,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -149,20 +145,16 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -182,12 +174,7 @@
 };
 
 &pio {
-	led_pins_cubieboard2: led_pins@0 {
-		pins = "PH20", "PH21";
-		function = "gpio_out";
-	};
-
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
@@ -239,7 +226,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-cubietruck.dts b/arch/arm/dts/sun7i-a20-cubietruck.dts
index 5649161..99f531b 100644
--- a/arch/arm/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/dts/sun7i-a20-cubietruck.dts
@@ -74,8 +74,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_cubietruck>;
 
 		blue {
 			label = "cubietruck:blue:usr";
@@ -100,9 +98,9 @@
 
 	mmc3_pwrseq: mmc3_pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		pinctrl-names = "default";
-		pinctrl-0 = <&mmc3_pwrseq_pin_cubietruck>;
 		reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
+		clocks = <&ccu CLK_OUT_A>;
+		clock-names = "ext_clock";
 	};
 
 	sound {
@@ -151,7 +149,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	status = "okay";
@@ -172,8 +170,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -185,25 +181,20 @@
 
 &i2c1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -211,8 +202,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	mmc-pwrseq = <&mmc3_pwrseq>;
 	bus-width = <4>;
@@ -228,11 +217,6 @@
 	};
 };
 
-&mmc3_pins_a {
-	/* AP6210 requires pull-up */
-	bias-pull-up;
-};
-
 &ohci0 {
 	status = "okay";
 };
@@ -246,45 +230,18 @@
 };
 
 &pio {
-	ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
-		pins = "PH12";
-		function = "gpio_out";
-	};
-
-	led_pins_cubietruck: led_pins@0 {
-		pins = "PH7", "PH11", "PH20", "PH21";
-		function = "gpio_out";
-	};
-
-	mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin@0 {
-		pins = "PH9";
-		function = "gpio_out";
-	};
-
-	usb0_vbus_pin_a: usb0_vbus_pin@0 {
-		pins = "PH17";
-		function = "gpio_out";
-	};
-
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
-		pins = "PH19";
-		function = "gpio_in";
-	};
-
-	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
-		pins = "PH22";
-		function = "gpio_in";
-	};
+	/* Pin outputs low power clock for WiFi and BT */
+	pinctrl-0 = <&clk_out_a_pin>;
+	pinctrl-names = "default";
 };
 
 &pwm {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>;
+	pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>;
 	status = "okay";
 };
 
 &reg_ahci_5v {
-	pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
 	gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -325,7 +282,6 @@
 };
 
 &reg_usb0_vbus {
-	pinctrl-0 = <&usb0_vbus_pin_a>;
 	gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -340,16 +296,33 @@
 
 &spdif {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spdif_tx_pins_a>;
+	pinctrl-0 = <&spdif_tx_pin>;
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm20702a1";
+		clocks = <&ccu CLK_OUT_A>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
+		host-wakeup-gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
+		shutdown-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */
+		max-speed = <1500000>;
+	};
+};
+
 &usb_otg {
 	dr_mode = "otg";
 	status = "okay";
@@ -360,8 +333,6 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
 	usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
 	usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
 	usb0_vbus_power-supply = <&usb_power_supply>;
diff --git a/arch/arm/dts/sun7i-a20-hummingbird.dts b/arch/arm/dts/sun7i-a20-hummingbird.dts
index 1f0e5ec..fd0153f 100644
--- a/arch/arm/dts/sun7i-a20-hummingbird.dts
+++ b/arch/arm/dts/sun7i-a20-hummingbird.dts
@@ -67,8 +67,6 @@
 
 	reg_mmc3_vdd: mmc3_vdd {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>;
 		regulator-name = "mmc3_vdd";
 		regulator-min-microvolt = <3000000>;
 		regulator-max-microvolt = <3000000>;
@@ -78,8 +76,6 @@
 
 	reg_gmac_vdd: gmac_vdd {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>;
 		regulator-name = "gmac_vdd";
 		regulator-min-microvolt = <3000000>;
 		regulator-max-microvolt = <3000000>;
@@ -103,7 +99,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_gmac_vdd>;
@@ -120,8 +116,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -135,32 +129,24 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
 &i2c3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c3_pins_a>;
 	status = "okay";
 };
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -168,8 +154,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>;
 	vmmc-supply = <&reg_mmc3_vdd>;
 	bus-width = <4>;
 	non-removable;
@@ -184,42 +168,18 @@
 	status = "okay";
 };
 
-&pio {
-	ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 {
-		pins = "PH15";
-		function = "gpio_out";
-	};
-
-	usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 {
-		pins = "PH2";
-		function = "gpio_out";
-	};
-
-	mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 {
-		pins = "PH9";
-		function = "gpio_out";
-	};
-
-	gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 {
-		pins = "PH16";
-		function = "gpio_out";
-	};
-};
-
 &pwm {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pwm0_pins_a>;
+	pinctrl-0 = <&pwm0_pin>;
 	status = "okay";
 };
 
 &reg_ahci_5v {
-	pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>;
 	gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
 	status = "okay";
 };
 
 &reg_usb1_vbus {
-	pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>;
 	gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
 	status = "okay";
 };
@@ -230,38 +190,38 @@
 
 &spi2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi2_pins_b>,
-		    <&spi2_cs0_pins_b>;
+	pinctrl-0 = <&spi2_pb_pins>,
+		    <&spi2_cs0_pb_pin>;
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
 &uart2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins_a>;
+	pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>;
 	status = "okay";
 };
 
 &uart3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins_a>;
+	pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>;
 	status = "okay";
 };
 
 &uart4 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_a>;
+	pinctrl-0 = <&uart4_pg_pins>;
 	status = "okay";
 };
 
 &uart5 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart5_pins_a>;
+	pinctrl-0 = <&uart5_pi_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/dts/sun7i-a20-i12-tvbox.dts
index 2e3f2f2..5f1c4f5 100644
--- a/arch/arm/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/dts/sun7i-a20-i12-tvbox.dts
@@ -61,8 +61,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_i12_tvbox>;
 
 		red {
 			label = "i12_tvbox:red:usr";
@@ -77,8 +75,6 @@
 
 	reg_vmmc3: vmmc3 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&vmmc3_pin_i12_tvbox>;
 		regulator-name = "vmmc3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -88,8 +84,6 @@
 
 	reg_vmmc3_io: vmmc3-io {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&vmmc3_io_pin_i12_tvbox>;
 		regulator-name = "vmmc3-io";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -101,8 +95,6 @@
 
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_power_pin_i12_tvbox>;
 		regulator-name = "gmac-3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -122,7 +114,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>;
+	pinctrl-0 = <&gmac_mii_pins>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	phy-supply = <&reg_gmac_3v3>;
@@ -134,8 +126,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -151,13 +141,11 @@
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -165,8 +153,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>;
 	vmmc-supply = <&reg_vmmc3>;
 	bus-width = <4>;
 	non-removable;
@@ -181,11 +167,6 @@
 	};
 };
 
-&mmc3_pins_a {
-	/* AP6210 / AP6330 requires pull-up */
-	bias-pull-up;
-};
-
 &ohci0 {
 	status = "okay";
 };
@@ -194,28 +175,6 @@
 	status = "okay";
 };
 
-&pio {
-	vmmc3_pin_i12_tvbox: vmmc3_pin@0 {
-		pins = "PH2";
-		function = "gpio_out";
-	};
-
-	vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 {
-		pins = "PH12";
-		function = "gpio_out";
-	};
-
-	gmac_power_pin_i12_tvbox: gmac_power_pin@0 {
-		pins = "PH21";
-		function = "gpio_out";
-	};
-
-	led_pins_i12_tvbox: led_pins@0 {
-		pins = "PH9", "PH20";
-		function = "gpio_out";
-	};
-};
-
 &reg_usb1_vbus {
 	status = "okay";
 };
@@ -226,7 +185,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-icnova-swac.dts b/arch/arm/dts/sun7i-a20-icnova-swac.dts
index 926fa19..9494947 100644
--- a/arch/arm/dts/sun7i-a20-icnova-swac.dts
+++ b/arch/arm/dts/sun7i-a20-icnova-swac.dts
@@ -74,7 +74,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>;
+	pinctrl-0 = <&gmac_mii_pins>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	status = "okay";
@@ -85,8 +85,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -97,14 +95,10 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */
@@ -156,7 +150,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-itead-ibox.dts b/arch/arm/dts/sun7i-a20-itead-ibox.dts
index 1b05ba4..b90a760 100644
--- a/arch/arm/dts/sun7i-a20-itead-ibox.dts
+++ b/arch/arm/dts/sun7i-a20-itead-ibox.dts
@@ -96,7 +96,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>;
+	pinctrl-0 = <&gmac_mii_pins>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	status = "okay";
@@ -115,13 +115,11 @@
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -129,7 +127,7 @@
 };
 
 &pio {
-	led_pins_itead_core: led_pins@0 {
+	led_pins_itead_core: led-pins {
 		pins = "PH20","PH21";
 		function = "gpio_out";
 		drive-strength = <20>;
@@ -142,6 +140,6 @@
 
 &spdif {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spdif_tx_pins_a>;
+	pinctrl-0 = <&spdif_tx_pin>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/dts/sun7i-a20-lamobo-r1.dts
index b1ab7c1..f91e1be 100644
--- a/arch/arm/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/dts/sun7i-a20-lamobo-r1.dts
@@ -74,8 +74,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_lamobo_r1>;
 
 		green {
 			label = "lamobo_r1:green:usr";
@@ -85,8 +83,6 @@
 
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_power_pin_lamobo_r1>;
 		regulator-name = "gmac-3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -123,10 +119,12 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_gmac_3v3>;
 	status = "okay";
+	/delete-property/#address-cells;
+	/delete-property/#size-cells;
 
 	fixed-link {
 		speed = <1000>;
@@ -141,8 +139,6 @@
 		switch: ethernet-switch@1e {
 			compatible = "brcm,bcm53125";
 			reg = <30>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 
 			ports {
 				#address-cells = <1>;
@@ -199,8 +195,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -211,20 +205,16 @@
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
@@ -240,27 +230,11 @@
 };
 
 &pio {
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
 	};
-
-	mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 {
-		pins = "PH10";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	gmac_power_pin_lamobo_r1: gmac_power_pin@0 {
-		pins = "PH23";
-		function = "gpio_out";
-	};
-
-	led_pins_lamobo_r1: led_pins@0 {
-		pins = "PH24";
-		function = "gpio_out";
-	};
 };
 
 #include "axp209.dtsi"
@@ -314,27 +288,27 @@
 
 &spi0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_pins_a>,
-		    <&spi0_cs0_pins_a>,
-		    <&spi0_cs1_pins_a>;
+	pinctrl-0 = <&spi0_pi_pins>,
+		    <&spi0_cs0_pi_pin>,
+		    <&spi0_cs1_pi_pin>;
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
 &uart3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins_b>;
+	pinctrl-0 = <&uart3_ph_pins>;
 	status = "okay";
 };
 
 &uart7 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart7_pins_a>;
+	pinctrl-0 = <&uart7_pi_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-m3.dts b/arch/arm/dts/sun7i-a20-m3.dts
index e91a209..b8a1aaa 100644
--- a/arch/arm/dts/sun7i-a20-m3.dts
+++ b/arch/arm/dts/sun7i-a20-m3.dts
@@ -63,8 +63,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_m3>;
 
 		blue {
 			label = "m3:blue:usr";
@@ -83,7 +81,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>;
+	pinctrl-0 = <&gmac_mii_pins>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	status = "okay";
@@ -94,8 +92,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -111,13 +107,11 @@
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -125,8 +119,6 @@
 };
 
 &mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	non-removable;
@@ -141,13 +133,6 @@
 	status = "okay";
 };
 
-&pio {
-	led_pins_m3: led_pins@0 {
-		pins = "PH20";
-		function = "gpio_out";
-	};
-};
-
 &reg_usb1_vbus {
 	status = "okay";
 };
@@ -158,7 +143,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-m5.dts b/arch/arm/dts/sun7i-a20-m5.dts
index 00c3ffd..6de52c7 100644
--- a/arch/arm/dts/sun7i-a20-m5.dts
+++ b/arch/arm/dts/sun7i-a20-m5.dts
@@ -21,6 +21,10 @@
 	};
 };
 
+&ahci {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -31,7 +35,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	status = "okay";
@@ -51,6 +55,6 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/sun7i-a20-mk808c.dts b/arch/arm/dts/sun7i-a20-mk808c.dts
index 6109f79..1491c60 100644
--- a/arch/arm/dts/sun7i-a20-mk808c.dts
+++ b/arch/arm/dts/sun7i-a20-mk808c.dts
@@ -106,8 +106,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -121,20 +119,14 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -153,18 +145,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
-		pins = "PH4";
-		function = "gpio_in";
-	};
-
-	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
-		pins = "PH5";
-		function = "gpio_in";
-	};
-};
-
 &reg_usb0_vbus {
 	status = "okay";
 };
@@ -179,13 +159,13 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
 &uart2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins_a>;
+	pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>;
 	status = "okay";
 };
 
@@ -195,8 +175,6 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
 	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
 	usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/dts/sun7i-a20-olimex-som-evb-emmc.dts
new file mode 100644
index 0000000..20bf09b
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olimex-som-evb-emmc.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som-evb.dts"
+
+/ {
+
+	model = "Olimex A20-Olimex-SOM-EVB-eMMC";
+	compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
+
+	mmc2_pwrseq: mmc2_pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&mmc2 {
+	vmmc-supply = <&reg_vcc3v3>;
+	mmc-pwrseq = <&mmc2_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	emmc: emmc@0 {
+		reg = <0>;
+		compatible = "mmc-card";
+		broken-hpi;
+	};
+};
diff --git a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
index f080f82..f0e6a96 100644
--- a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
@@ -74,8 +74,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_olimex_som_evb>;
 
 		green {
 			label = "a20-olimex-som-evb:green:usr";
@@ -112,7 +110,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	status = "okay";
@@ -133,8 +131,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -145,14 +141,10 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
@@ -160,49 +152,49 @@
 	vref-supply = <&reg_vcc3v0>;
 	status = "okay";
 
-	button@190 {
+	button-190 {
 		label = "Volume Up";
 		linux,code = <KEY_VOLUMEUP>;
 		channel = <0>;
 		voltage = <190000>;
 	};
 
-	button@390 {
+	button-390 {
 		label = "Volume Down";
 		linux,code = <KEY_VOLUMEDOWN>;
 		channel = <0>;
 		voltage = <390000>;
 	};
 
-	button@600 {
+	button-600 {
 		label = "Menu";
 		linux,code = <KEY_MENU>;
 		channel = <0>;
 		voltage = <600000>;
 	};
 
-	button@800 {
+	button-800 {
 		label = "Search";
 		linux,code = <KEY_SEARCH>;
 		channel = <0>;
 		voltage = <800000>;
 	};
 
-	button@980 {
+	button-980 {
 		label = "Home";
 		linux,code = <KEY_HOMEPAGE>;
 		channel = <0>;
 		voltage = <980000>;
 	};
 
-	button@1180 {
+	button-1180 {
 		label = "Esc";
 		linux,code = <KEY_ESC>;
 		channel = <0>;
 		voltage = <1180000>;
 	};
 
-	button@1400 {
+	button-1400 {
 		label = "Enter";
 		linux,code = <KEY_ENTER>;
 		channel = <0>;
@@ -211,8 +203,6 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -220,8 +210,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */
@@ -241,36 +229,14 @@
 };
 
 &pio {
-	ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin@1 {
-		pins = "PC3";
-		function = "gpio_out";
-	};
-
-	led_pins_olimex_som_evb: led_pins@0 {
+	led_pins_olimex_som_evb: led-pins {
 		pins = "PH2";
 		function = "gpio_out";
 		drive-strength = <20>;
 	};
-
-	mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin@0 {
-		pins = "PH0";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
-		pins = "PH4";
-		function = "gpio_in";
-	};
-
-	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
-		pins = "PH5";
-		function = "gpio_in";
-	};
 };
 
 &reg_ahci_5v {
-	pinctrl-0 = <&ahci_pwr_pin_olimex_som_evb>;
 	gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -316,33 +282,33 @@
 
 &spi1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins_a>,
-		    <&spi1_cs0_pins_a>;
+	pinctrl-0 = <&spi1_pi_pins>,
+		    <&spi1_cs0_pi_pin>;
 	status = "okay";
 };
 
 &spi2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi2_pins_a>,
-		    <&spi2_cs0_pins_a>;
+	pinctrl-0 = <&spi2_pc_pins>,
+		    <&spi2_cs0_pc_pin>;
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
 &uart6 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart6_pins_a>;
+	pinctrl-0 = <&uart6_pi_pins>;
 	status = "okay";
 };
 
 &uart7 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart7_pins_a>;
+	pinctrl-0 = <&uart7_pi_pins>;
 	status = "okay";
 };
 
@@ -352,8 +318,6 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
 	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */
 	usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
index c56620a..a59755a 100644
--- a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
@@ -20,8 +20,6 @@
 };
 
 &mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	mmc-pwrseq = <&mmc2_pwrseq>;
 	bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
index 3d7b5c8..823aabc 100644
--- a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
@@ -78,7 +78,7 @@
 
 &can0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&can0_pins_a>;
+	pinctrl-0 = <&can_ph_pins>;
 	status = "okay";
 };
 
@@ -104,7 +104,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy3>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_vcc3v3>;
@@ -130,8 +130,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -143,8 +141,6 @@
 
 /* Exposed to UEXT1 */
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 
 	eeprom: eeprom@50 {
@@ -156,20 +152,16 @@
 
 /* Exposed to UEXT2 */
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>;
@@ -177,8 +169,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	mmc-pwrseq = <&rtl_pwrseq>;
 	bus-width = <4>;
@@ -203,8 +193,8 @@
 };
 
 &pio {
-	bt_uart_pins: bt_uart_pins@0 {
-		pins = "PG6", "PG7", "PG8";
+	uart3_rts_pin: uart3-rts-pin {
+		pins = "PG8";
 		function = "uart3";
 	};
 };
@@ -274,43 +264,43 @@
 /* Exposed to UEXT1 */
 &spi1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins_a>,
-		    <&spi1_cs0_pins_a>;
+	pinctrl-0 = <&spi1_pi_pins>,
+		    <&spi1_cs0_pi_pin>;
 	status = "okay";
 };
 
 /* Exposed to UEXT2 */
 &spi2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi2_pins_a>,
-		    <&spi2_cs0_pins_a>;
+	pinctrl-0 = <&spi2_pc_pins>,
+		    <&spi2_cs0_pc_pin>;
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
 /* Used for RTL8723BS bluetooth */
 &uart3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&bt_uart_pins>;
+	pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_pin>;
 	status = "okay";
 };
 
 /* Exposed to UEXT1 */
 &uart4 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_a>;
+	pinctrl-0 = <&uart4_pg_pins>;
 	status = "okay";
 };
 
 /* Exposed to UEXT2 */
 &uart7 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart7_pins_a>;
+	pinctrl-0 = <&uart7_pi_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
index d20fd03..5e41119 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
@@ -105,7 +105,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>;
+	pinctrl-0 = <&gmac_mii_pins>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	status = "okay";
@@ -126,8 +126,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -142,8 +140,6 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 
 	eeprom: eeprom@50 {
@@ -154,8 +150,6 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -175,24 +169,19 @@
 };
 
 &pio {
-	ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
-		pins = "PC3";
-		function = "gpio_out";
-	};
-
-	led_pins_olinuxinolime: led_pins@0 {
+	led_pins_olinuxinolime: led-pins {
 		pins = "PH2";
 		function = "gpio_out";
 		drive-strength = <20>;
 	};
 
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
 	};
 
-	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
 		pins = "PH5";
 		function = "gpio_in";
 		bias-pull-down;
@@ -200,7 +189,6 @@
 };
 
 &reg_ahci_5v {
-	pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
 	gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -219,7 +207,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts
index 81f376f..decb014 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts
@@ -48,23 +48,12 @@
 	compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20";
 
 	mmc2_pwrseq: pwrseq {
-		pinctrl-0 = <&mmc2_pins_nrst>;
-		pinctrl-names = "default";
 		compatible = "mmc-pwrseq-emmc";
 		reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
 	};
 };
 
-&pio {
-	mmc2_pins_nrst: mmc2-rst-pin {
-		pins = "PC16";
-		function = "gpio_out";
-	};
-};
-
 &mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	vqmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
index b828677..4e1c590 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
@@ -110,7 +110,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	status = "okay";
@@ -131,8 +131,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -143,8 +141,6 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 
 	eeprom: eeprom@50 {
@@ -154,9 +150,11 @@
 	};
 };
 
+&lradc {
+	vref-supply = <&reg_vcc3v0>;
+};
+
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -176,37 +174,26 @@
 };
 
 &pio {
-	ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
-		pins = "PC3";
-		function = "gpio_out";
-	};
-
-	led_pins_olinuxinolime: led_pins@0 {
+	led_pins_olinuxinolime: led-pins {
 		pins = "PH2";
 		function = "gpio_out";
 		drive-strength = <20>;
 	};
 
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
 	};
 
-	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
 		pins = "PH5";
 		function = "gpio_in";
 		bias-pull-down;
 	};
-
-	usb0_vbus_pin_lime2: usb0_vbus_pin@0 {
-		pins = "PC17";
-		function = "gpio_out";
-	};
 };
 
 &reg_ahci_5v {
-	pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
 	gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -245,6 +232,8 @@
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <2800000>;
 	regulator-name = "vddio-csi0";
+	regulator-soft-start;
+	regulator-ramp-delay = <1600>;
 };
 
 &reg_ldo4 {
@@ -254,7 +243,6 @@
 };
 
 &reg_usb0_vbus {
-	pinctrl-0 = <&usb0_vbus_pin_lime2>;
 	gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -269,7 +257,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
index d99e7b1..2337b44 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts
@@ -54,8 +54,6 @@
 };
 
 &mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	non-removable;
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
index 866d230..840ae11 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
@@ -117,7 +117,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>, <&gmac_txerr>;
+	pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	status = "okay";
@@ -138,8 +138,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -150,8 +148,6 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 
 	eeprom: eeprom@50 {
@@ -162,8 +158,6 @@
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
@@ -171,49 +165,49 @@
 	vref-supply = <&reg_vcc3v0>;
 	status = "okay";
 
-	button@191 {
+	button-191 {
 		label = "Volume Up";
 		linux,code = <KEY_VOLUMEUP>;
 		channel = <0>;
 		voltage = <191274>;
 	};
 
-	button@392 {
+	button-392 {
 		label = "Volume Down";
 		linux,code = <KEY_VOLUMEDOWN>;
 		channel = <0>;
 		voltage = <392644>;
 	};
 
-	button@601 {
+	button-601 {
 		label = "Menu";
 		linux,code = <KEY_MENU>;
 		channel = <0>;
 		voltage = <601151>;
 	};
 
-	button@795 {
+	button-795 {
 		label = "Search";
 		linux,code = <KEY_SEARCH>;
 		channel = <0>;
 		voltage = <795090>;
 	};
 
-	button@987 {
+	button-987 {
 		label = "Home";
 		linux,code = <KEY_HOMEPAGE>;
 		channel = <0>;
 		voltage = <987387>;
 	};
 
-	button@1184 {
+	button-1184 {
 		label = "Esc";
 		linux,code = <KEY_ESC>;
 		channel = <0>;
 		voltage = <1184678>;
 	};
 
-	button@1398 {
+	button-1398 {
 		label = "Enter";
 		linux,code = <KEY_ENTER>;
 		channel = <0>;
@@ -222,8 +216,6 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -231,8 +223,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
@@ -252,30 +242,24 @@
 };
 
 &pio {
-	gmac_txerr: gmac_txerr@0 {
+	gmac_txerr: gmac-txerr-pin {
 		pins = "PA17";
 		function = "gmac";
 	};
 
-	mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
-		pins = "PH11";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	led_pins_olinuxino: led_pins@0 {
+	led_pins_olinuxino: led-pins {
 		pins = "PH2";
 		function = "gpio_out";
 		drive-strength = <20>;
 	};
 
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
 	};
 
-	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
 		pins = "PH5";
 		function = "gpio_in";
 		bias-pull-down;
@@ -331,33 +315,33 @@
 
 &spi1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins_a>,
-		    <&spi1_cs0_pins_a>;
+	pinctrl-0 = <&spi1_pi_pins>,
+		    <&spi1_cs0_pi_pin>;
 	status = "okay";
 };
 
 &spi2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi2_pins_a>,
-		    <&spi2_cs0_pins_a>;
+	pinctrl-0 = <&spi2_pc_pins>,
+		    <&spi2_cs0_pc_pin>;
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
 &uart6 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart6_pins_a>;
+	pinctrl-0 = <&uart6_pi_pins>;
 	status = "okay";
 };
 
 &uart7 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart7_pins_a>;
+	pinctrl-0 = <&uart7_pi_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/dts/sun7i-a20-orangepi-mini.dts
index f5c7178..1588108 100644
--- a/arch/arm/dts/sun7i-a20-orangepi-mini.dts
+++ b/arch/arm/dts/sun7i-a20-orangepi-mini.dts
@@ -74,8 +74,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_orangepi>;
 
 		green {
 			label = "orangepi:green:usr";
@@ -90,8 +88,6 @@
 
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_power_pin_orangepi>;
 		regulator-name = "gmac-3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -123,7 +119,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_gmac_3v3>;
@@ -145,8 +141,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -160,13 +154,11 @@
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
@@ -174,8 +166,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
@@ -187,43 +177,11 @@
 };
 
 &pio {
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
 	};
-
-	mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
-		pins = "PH10";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	mmc3_cd_pin_orangepi: mmc3_cd_pin@0 {
-		pins = "PH11";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
-		pins = "PH22";
-		function = "gpio_out";
-	};
-
-	gmac_power_pin_orangepi: gmac_power_pin@0 {
-		pins = "PH23";
-		function = "gpio_out";
-	};
-
-	led_pins_orangepi: led_pins@0 {
-		pins = "PH24", "PH25";
-		function = "gpio_out";
-	};
-
-	usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
-		pins = "PH26";
-		function = "gpio_out";
-	};
 };
 
 &reg_dcdc2 {
@@ -256,20 +214,18 @@
 };
 
 &reg_usb1_vbus {
-	pinctrl-0 = <&usb1_vbus_pin_bananapro>;
 	gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */
 	status = "okay";
 };
 
 &reg_usb2_vbus {
-	pinctrl-0 = <&usb2_vbus_pin_bananapro>;
 	gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-orangepi.dts b/arch/arm/dts/sun7i-a20-orangepi.dts
index 7a4244e..d64de2e 100644
--- a/arch/arm/dts/sun7i-a20-orangepi.dts
+++ b/arch/arm/dts/sun7i-a20-orangepi.dts
@@ -63,8 +63,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_orangepi>;
 
 		green {
 			label = "orangepi:green:usr";
@@ -74,8 +72,6 @@
 
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gmac_power_pin_orangepi>;
 		regulator-name = "gmac-3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -99,7 +95,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_gmac_3v3>;
@@ -111,8 +107,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -126,13 +120,11 @@
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
@@ -144,37 +136,11 @@
 };
 
 &pio {
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
 	};
-
-	mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
-		pins = "PH10";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
-		pins = "PH22";
-		function = "gpio_out";
-	};
-
-	gmac_power_pin_orangepi: gmac_power_pin@0 {
-		pins = "PH23";
-		function = "gpio_out";
-	};
-
-	led_pins_orangepi: led_pins@0 {
-		pins = "PH24";
-		function = "gpio_out";
-	};
-
-	usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
-		pins = "PH26";
-		function = "gpio_out";
-	};
 };
 
 &reg_dcdc2 {
@@ -207,20 +173,18 @@
 };
 
 &reg_usb1_vbus {
-	pinctrl-0 = <&usb1_vbus_pin_bananapro>;
 	gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */
 	status = "okay";
 };
 
 &reg_usb2_vbus {
-	pinctrl-0 = <&usb2_vbus_pin_bananapro>;
 	gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
index bfca960..538ea15 100644
--- a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
@@ -71,8 +71,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_pcduino3_nano>;
 
 		/* Marked "LED3" on the PCB. */
 		usr1 {
@@ -115,7 +113,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	status = "okay";
@@ -136,8 +134,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -149,13 +145,11 @@
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -175,30 +169,14 @@
 };
 
 &pio {
-	ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 {
-		pins = "PH2";
-		function = "gpio_out";
-	};
-
-	led_pins_pcduino3_nano: led_pins@0 {
-		pins = "PH16", "PH15";
-		function = "gpio_out";
-	};
-
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
 	};
-
-	usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
-		pins = "PD2";
-		function = "gpio_out";
-	};
 };
 
 &reg_ahci_5v {
-	pinctrl-0 = <&ahci_pwr_pin_pcduino3_nano>;
 	gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
 	status = "okay";
 };
@@ -232,14 +210,13 @@
 
 /* A single regulator (U24) powers both USB host ports. */
 &reg_usb1_vbus {
-	pinctrl-0 = <&usb1_vbus_pin_pcduino3_nano>;
 	gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
 	status = "okay";
 };
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
index c576f10..a72ed43 100644
--- a/arch/arm/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -63,8 +63,6 @@
 
 	leds {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_pcduino3>;
 
 		tx {
 			label = "pcduino3:green:tx";
@@ -77,23 +75,22 @@
 		};
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&key_pins_pcduino3>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		button@0 {
+
+		back {
 			label = "Key Back";
 			linux,code = <KEY_BACK>;
 			gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
 		};
-		button@1 {
+
+		home {
 			label = "Key Home";
 			linux,code = <KEY_HOME>;
 			gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+
+		menu {
 			label = "Key Menu";
 			linux,code = <KEY_MENU>;
 			gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
@@ -124,7 +121,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_mii_a>;
+	pinctrl-0 = <&gmac_mii_pins>;
 	phy = <&phy1>;
 	phy-mode = "mii";
 	status = "okay";
@@ -135,8 +132,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -150,13 +145,11 @@
 
 &ir0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&ir0_rx_pins_a>;
+	pinctrl-0 = <&ir0_rx_pin>;
 	status = "okay";
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -176,17 +169,7 @@
 };
 
 &pio {
-	led_pins_pcduino3: led_pins@0 {
-		pins = "PH15", "PH16";
-		function = "gpio_out";
-	};
-
-	key_pins_pcduino3: key_pins@0 {
-		pins = "PH17", "PH18", "PH19";
-		function = "gpio_in";
-	};
-
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
@@ -233,7 +216,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-primo73.dts b/arch/arm/dts/sun7i-a20-primo73.dts
index b7294e0..ac0175f 100644
--- a/arch/arm/dts/sun7i-a20-primo73.dts
+++ b/arch/arm/dts/sun7i-a20-primo73.dts
@@ -67,8 +67,6 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -82,7 +80,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
index 8202c87..ffade25 100644
--- a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
@@ -63,8 +63,6 @@
 		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&bl_enable_pin>;
 		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
 	};
 
@@ -74,8 +72,6 @@
 };
 
 &codec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&codec_pa_pin>;
 	allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
 	status = "okay";
 };
@@ -93,8 +89,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -107,14 +101,10 @@
 #include "axp209.dtsi"
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 
 	gt911: touchscreen@5d {
@@ -122,8 +112,6 @@
 		reg = <0x5d>;
 		interrupt-parent = <&pio>;
 		interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */
-		pinctrl-names = "default";
-		pinctrl-0 = <&ts_reset_pin>;
 		irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */
 		reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */
 		touchscreen-swapped-x-y;
@@ -134,14 +122,14 @@
 	vref-supply = <&reg_vcc3v0>;
 	status = "okay";
 
-	button@571 {
+	button-571 {
 		label = "Volume Up";
 		linux,code = <KEY_VOLUMEUP>;
 		channel = <0>;
 		voltage = <571428>;
 	};
 
-	button@761 {
+	button-761 {
 		label = "Volume Down";
 		linux,code = <KEY_VOLUMEDOWN>;
 		channel = <0>;
@@ -150,8 +138,6 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -171,22 +157,7 @@
 };
 
 &pio {
-	bl_enable_pin: bl_enable_pin@0 {
-		pins = "PH7";
-		function = "gpio_out";
-	};
-
-	codec_pa_pin: codec_pa_pin@0 {
-		pins = "PH15";
-		function = "gpio_out";
-	};
-
-	ts_reset_pin: ts_reset_pin@0 {
-		pins = "PB13";
-		function = "gpio_out";
-	};
-
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
@@ -195,7 +166,7 @@
 
 &pwm {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pwm0_pins_a>;
+	pinctrl-0 = <&pwm0_pin>;
 	status = "okay";
 };
 
@@ -238,7 +209,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt-u-boot.dtsi b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt-u-boot.dtsi
new file mode 100644
index 0000000..8a1c468
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "sunxi-u-boot.dtsi"
+
+&ahci {
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
index ff5c108..c27e560 100644
--- a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
+++ b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
@@ -62,8 +62,6 @@
 
 	mmc3_pwrseq: mmc3_pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		pinctrl-names = "default";
-		pinctrl-0 = <&vmmc3_pin_ap6xxx_wl_regon>;
 		reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
 	};
 };
@@ -82,7 +80,7 @@
 
 &gmac {
 	pinctrl-names = "default";
-	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy = <&phy1>;
 	phy-mode = "rgmii";
 	status = "okay";
@@ -93,8 +91,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -105,22 +101,16 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
 &i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
 };
 
 #include "axp209.dtsi"
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
@@ -128,8 +118,6 @@
 };
 
 &mmc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	mmc-pwrseq = <&mmc3_pwrseq>;
 	bus-width = <4>;
@@ -158,12 +146,7 @@
 };
 
 &pio {
-	vmmc3_pin_ap6xxx_wl_regon: vmmc3_pin@0 {
-		pins = "PH9";
-		function = "gpio_out";
-	};
-
-	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+	usb0_id_detect_pin: usb0-id-detect-pin {
 		pins = "PH4";
 		function = "gpio_in";
 		bias-pull-up;
@@ -209,7 +192,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts b/arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts
index f1fb97d..11142ae 100644
--- a/arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts
+++ b/arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts
@@ -23,6 +23,6 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
index e529e4f..641a8fa 100644
--- a/arch/arm/dts/sun7i-a20.dtsi
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -42,8 +42,6 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
-
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/dma/sun4i-a10.h>
@@ -52,6 +50,8 @@
 
 / {
 	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
 
 	aliases {
 		ethernet0 = &gmac;
@@ -62,7 +62,7 @@
 		#size-cells = <1>;
 		ranges;
 
-		framebuffer@0 {
+		framebuffer-lcd0-hdmi {
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-hdmi";
@@ -73,7 +73,7 @@
 			status = "disabled";
 		};
 
-		framebuffer@1 {
+		framebuffer-lcd0 {
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0";
@@ -83,7 +83,7 @@
 			status = "disabled";
 		};
 
-		framebuffer@2 {
+		framebuffer-lcd0-tve0 {
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-tve0";
@@ -118,10 +118,23 @@
 			#cooling-cells = <2>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <1>;
+			clocks = <&ccu CLK_CPU>;
+			clock-latency = <244144>; /* 8 32k periods */
+			operating-points = <
+				/* kHz	  uV */
+				960000	1400000
+				912000	1400000
+				864000	1300000
+				720000	1200000
+				528000	1100000
+				312000	1000000
+				144000	1000000
+				>;
+			#cooling-cells = <2>;
 		};
 	};
 
@@ -135,7 +148,8 @@
 			cooling-maps {
 				map0 {
 					trip = <&cpu_alert0>;
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 
@@ -157,8 +171,19 @@
 		};
 	};
 
-	memory {
-		reg = <0x40000000 0x80000000>;
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+		default-pool {
+			compatible = "shared-dma-pool";
+			size = <0x6000000>;
+			alloc-ranges = <0x4a000000 0x6000000>;
+			reusable;
+			linux,cma-default;
+		};
 	};
 
 	timer {
@@ -170,7 +195,7 @@
 	};
 
 	pmu {
-		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+		compatible = "arm,cortex-a7-pmu";
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 	};
@@ -180,14 +205,14 @@
 		#size-cells = <1>;
 		ranges;
 
-		osc24M: clk@1c20050 {
+		osc24M: clk-24M {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
 			clock-output-names = "osc24M";
 		};
 
-		osc32k: clk@0 {
+		osc32k: clk-32k {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
@@ -203,14 +228,14 @@
 		 * The actual TX clock rate is not controlled by the
 		 * gmac_tx clock.
 		 */
-		mii_phy_tx_clk: clk@1 {
+		mii_phy_tx_clk: clk-mii-phy-tx {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <25000000>;
 			clock-output-names = "mii_phy_tx";
 		};
 
-		gmac_int_tx_clk: clk@2 {
+		gmac_int_tx_clk: clk-gmac-int-tx {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <125000000>;
@@ -233,14 +258,15 @@
 		status = "disabled";
 	};
 
-	soc@1c00000 {
+	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
-		sram-controller@1c00000 {
-			compatible = "allwinner,sun4i-a10-sram-controller";
+		system-control@1c00000 {
+			compatible = "allwinner,sun7i-a20-system-control",
+				     "allwinner,sun4i-a10-system-control";
 			reg = <0x01c00000 0x30>;
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -254,7 +280,8 @@
 				ranges = <0 0x00000000 0xc000>;
 
 				emac_sram: sram-section@8000 {
-					compatible = "allwinner,sun4i-a10-sram-a3-a4";
+					compatible = "allwinner,sun7i-a20-sram-a3-a4",
+						     "allwinner,sun4i-a10-sram-a3-a4";
 					reg = <0x8000 0x4000>;
 					status = "disabled";
 				};
@@ -268,11 +295,26 @@
 				ranges = <0 0x00010000 0x1000>;
 
 				otg_sram: sram-section@0 {
-					compatible = "allwinner,sun4i-a10-sram-d";
+					compatible = "allwinner,sun7i-a20-sram-d",
+						     "allwinner,sun4i-a10-sram-d";
 					reg = <0x0000 0x1000>;
 					status = "disabled";
 				};
 			};
+
+			sram_c: sram@1d00000 {
+				compatible = "mmio-sram";
+				reg = <0x01d00000 0xd0000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x01d00000 0xd0000>;
+
+				ve_sram: sram-section@0 {
+					compatible = "allwinner,sun7i-a20-sram-c1",
+						     "allwinner,sun4i-a10-sram-c1";
+					reg = <0x000000 0x80000>;
+				};
+			};
 		};
 
 		nmi_intc: interrupt-controller@1c00030 {
@@ -449,6 +491,17 @@
 			};
 		};
 
+		video-codec@1c0e000 {
+			compatible = "allwinner,sun7i-a20-video-engine";
+			reg = <0x01c0e000 0x1000>;
+			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+				 <&ccu CLK_DRAM_VE>;
+			clock-names = "ahb", "mod", "ram";
+			resets = <&ccu RST_VE>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			allwinner,sram = <&ve_sram 1>;
+		};
+
 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
@@ -461,6 +514,8 @@
 				      "output",
 				      "sample";
 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -495,6 +550,8 @@
 				      "output",
 				      "sample";
 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc2_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -512,6 +569,8 @@
 				      "output",
 				      "sample";
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc3_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -609,8 +668,6 @@
 				};
 
 				hdmi_out: port@1 {
-					#address-cells = <1>;
-					#size-cells = <0>;
 					reg = <1>;
 				};
 			};
@@ -694,22 +751,22 @@
 			#interrupt-cells = <3>;
 			#gpio-cells = <3>;
 
-			can0_pins_a: can0@0 {
+			can_ph_pins: can-ph-pins {
 				pins = "PH20", "PH21";
 				function = "can";
 			};
 
-			clk_out_a_pins_a: clk_out_a@0 {
+			clk_out_a_pin: clk-out-a-pin {
 				pins = "PI12";
 				function = "clk_out_a";
 			};
 
-			clk_out_b_pins_a: clk_out_b@0 {
+			clk_out_b_pin: clk-out-b-pin {
 				pins = "PI13";
 				function = "clk_out_b";
 			};
 
-			emac_pins_a: emac0@0 {
+			emac_pa_pins: emac-pa-pins {
 				pins = "PA0", "PA1", "PA2",
 				       "PA3", "PA4", "PA5", "PA6",
 				       "PA7", "PA8", "PA9", "PA10",
@@ -718,7 +775,7 @@
 				function = "emac";
 			};
 
-			gmac_pins_mii_a: gmac_mii@0 {
+			gmac_mii_pins: gmac-mii-pins {
 				pins = "PA0", "PA1", "PA2",
 				       "PA3", "PA4", "PA5", "PA6",
 				       "PA7", "PA8", "PA9", "PA10",
@@ -727,7 +784,7 @@
 				function = "gmac";
 			};
 
-			gmac_pins_rgmii_a: gmac_rgmii@0 {
+			gmac_rgmii_pins: gmac-rgmii-pins {
 				pins = "PA0", "PA1", "PA2",
 				       "PA3", "PA4", "PA5", "PA6",
 				        "PA7", "PA8", "PA10",
@@ -741,47 +798,47 @@
 				drive-strength = <40>;
 			};
 
-			i2c0_pins_a: i2c0@0 {
+			i2c0_pins: i2c0-pins {
 				pins = "PB0", "PB1";
 				function = "i2c0";
 			};
 
-			i2c1_pins_a: i2c1@0 {
+			i2c1_pins: i2c1-pins {
 				pins = "PB18", "PB19";
 				function = "i2c1";
 			};
 
-			i2c2_pins_a: i2c2@0 {
+			i2c2_pins: i2c2-pins {
 				pins = "PB20", "PB21";
 				function = "i2c2";
 			};
 
-			i2c3_pins_a: i2c3@0 {
+			i2c3_pins: i2c3-pins {
 				pins = "PI0", "PI1";
 				function = "i2c3";
 			};
 
-			ir0_rx_pins_a: ir0@0 {
+			ir0_rx_pin: ir0-rx-pin {
 				pins = "PB4";
 				function = "ir0";
 			};
 
-			ir0_tx_pins_a: ir0@1 {
+			ir0_tx_pin: ir0-tx-pin {
 				pins = "PB3";
 				function = "ir0";
 			};
 
-			ir1_rx_pins_a: ir1@0 {
+			ir1_rx_pin: ir1-rx-pin {
 				pins = "PB23";
 				function = "ir1";
 			};
 
-			ir1_tx_pins_a: ir1@1 {
+			ir1_tx_pin: ir1-tx-pin {
 				pins = "PB22";
 				function = "ir1";
 			};
 
-			mmc0_pins_a: mmc0@0 {
+			mmc0_pins: mmc0-pins {
 				pins = "PF0", "PF1", "PF2",
 				       "PF3", "PF4", "PF5";
 				function = "mmc0";
@@ -789,7 +846,7 @@
 				bias-pull-up;
 			};
 
-			mmc2_pins_a: mmc2@0 {
+			mmc2_pins: mmc2-pins {
 				pins = "PC6", "PC7", "PC8",
 				       "PC9", "PC10", "PC11";
 				function = "mmc2";
@@ -797,7 +854,7 @@
 				bias-pull-up;
 			};
 
-			mmc3_pins_a: mmc3@0 {
+			mmc3_pins: mmc3-pins {
 				pins = "PI4", "PI5", "PI6",
 				       "PI7", "PI8", "PI9";
 				function = "mmc3";
@@ -805,118 +862,128 @@
 				bias-pull-up;
 			};
 
-			ps20_pins_a: ps20@0 {
+			ps2_0_pins: ps2-0-pins {
 				pins = "PI20", "PI21";
 				function = "ps2";
 			};
 
-			ps21_pins_a: ps21@0 {
+			ps2_1_ph_pins: ps2-1-ph-pins {
 				pins = "PH12", "PH13";
 				function = "ps2";
 			};
 
-			pwm0_pins_a: pwm0@0 {
+			pwm0_pin: pwm0-pin {
 				pins = "PB2";
 				function = "pwm";
 			};
 
-			pwm1_pins_a: pwm1@0 {
+			pwm1_pin: pwm1-pin {
 				pins = "PI3";
 				function = "pwm";
 			};
 
-			spdif_tx_pins_a: spdif@0 {
+			spdif_tx_pin: spdif-tx-pin {
 				pins = "PB13";
 				function = "spdif";
 				bias-pull-up;
 			};
 
-			spi0_pins_a: spi0@0 {
+			spi0_pi_pins: spi0-pi-pins {
 				pins = "PI11", "PI12", "PI13";
 				function = "spi0";
 			};
 
-			spi0_cs0_pins_a: spi0_cs0@0 {
+			spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 				pins = "PI10";
 				function = "spi0";
 			};
 
-			spi0_cs1_pins_a: spi0_cs1@0 {
+			spi0_cs1_pi_pin: spi0-cs1-pi-pin {
 				pins = "PI14";
 				function = "spi0";
 			};
 
-			spi1_pins_a: spi1@0 {
+			spi1_pi_pins: spi1-pi-pins {
 				pins = "PI17", "PI18", "PI19";
 				function = "spi1";
 			};
 
-			spi1_cs0_pins_a: spi1_cs0@0 {
+			spi1_cs0_pi_pin: spi1-cs0-pi-pin {
 				pins = "PI16";
 				function = "spi1";
 			};
 
-			spi2_pins_a: spi2@0 {
-				pins = "PC20", "PC21", "PC22";
-				function = "spi2";
-			};
-
-			spi2_pins_b: spi2@1 {
+			spi2_pb_pins: spi2-pb-pins {
 				pins = "PB15", "PB16", "PB17";
 				function = "spi2";
 			};
 
-			spi2_cs0_pins_a: spi2_cs0@0 {
-				pins = "PC19";
-				function = "spi2";
-			};
-
-			spi2_cs0_pins_b: spi2_cs0@1 {
+			spi2_cs0_pb_pin: spi2-cs0-pb-pin {
 				pins = "PB14";
 				function = "spi2";
 			};
 
-			uart0_pins_a: uart0@0 {
+			spi2_pc_pins: spi2-pc-pins {
+				pins = "PC20", "PC21", "PC22";
+				function = "spi2";
+			};
+
+			spi2_cs0_pc_pin: spi2-cs0-pc-pin {
+				pins = "PC19";
+				function = "spi2";
+			};
+
+			uart0_pb_pins: uart0-pb-pins {
 				pins = "PB22", "PB23";
 				function = "uart0";
 			};
 
-			uart2_pins_a: uart2@0 {
-				pins = "PI16", "PI17", "PI18", "PI19";
+			uart2_pi_pins: uart2-pi-pins {
+				pins = "PI18", "PI19";
 				function = "uart2";
 			};
 
-			uart3_pins_a: uart3@0 {
-				pins = "PG6", "PG7", "PG8", "PG9";
+			uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
+				pins = "PI16", "PI17";
+				function = "uart2";
+			};
+
+			uart3_pg_pins: uart3-pg-pins {
+				pins = "PG6", "PG7";
 				function = "uart3";
 			};
 
-			uart3_pins_b: uart3@1 {
+			uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
+				pins = "PG8", "PG9";
+				function = "uart3";
+			};
+
+			uart3_ph_pins: uart3-ph-pins {
 				pins = "PH0", "PH1";
 				function = "uart3";
 			};
 
-			uart4_pins_a: uart4@0 {
+			uart4_pg_pins: uart4-pg-pins {
 				pins = "PG10", "PG11";
 				function = "uart4";
 			};
 
-			uart4_pins_b: uart4@1 {
+			uart4_ph_pins: uart4-ph-pins {
 				pins = "PH4", "PH5";
 				function = "uart4";
 			};
 
-			uart5_pins_a: uart5@0 {
+			uart5_pi_pins: uart5-pi-pins {
 				pins = "PI10", "PI11";
 				function = "uart5";
 			};
 
-			uart6_pins_a: uart6@0 {
+			uart6_pi_pins: uart6-pi-pins {
 				pins = "PI12", "PI13";
 				function = "uart6";
 			};
 
-			uart7_pins_a: uart7@0 {
+			uart7_pi_pins: uart7-pi-pins {
 				pins = "PI20", "PI21";
 				function = "uart7";
 			};
@@ -1157,6 +1224,8 @@
 			reg = <0x01c2ac00 0x400>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_APB1_I2C0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1168,6 +1237,8 @@
 			reg = <0x01c2b000 0x400>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_APB1_I2C1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1179,6 +1250,8 @@
 			reg = <0x01c2b400 0x400>;
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_APB1_I2C2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1190,6 +1263,8 @@
 			reg = <0x01c2b800 0x400>;
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_APB1_I2C3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c3_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
index 25fb048..c488aaa 100644
--- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -59,6 +59,17 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -91,9 +102,21 @@
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+		clocks = <&ccu CLK_OUTA>;
+		clock-names = "ext_clock";
 	};
 };
 
+&ahci {
+	ahci-supply = <&reg_dldo4>;
+	phy-supply = <&reg_eldo3>;
+	status = "okay";
+};
+
+&de {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -118,6 +141,16 @@
 	};
 };
 
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -134,8 +167,7 @@
 &mmc0 {
 	vmmc-supply = <&reg_dcdc1>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
-	cd-inverted;
+	cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
 	status = "okay";
 };
 
@@ -166,6 +198,11 @@
 	status = "okay";
 };
 
+&pio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&clk_out_a_pin>;
+};
+
 &reg_aldo2 {
 	regulator-always-on;
 	regulator-min-microvolt = <2500000>;
@@ -220,18 +257,68 @@
 	regulator-name = "vcc-wifi-io";
 };
 
+/*
+ * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same
+ * time, with the two being in sync, to be able to meet maximum power
+ * consumption during transmits. Since this is not really supported
+ * right now, just use the two as always on, and we will fix it later.
+ */
+
 &reg_dldo2 {
+	regulator-always-on;
 	regulator-min-microvolt = <3300000>;
 	regulator-max-microvolt = <3300000>;
 	regulator-name = "vcc-wifi";
 };
 
+&reg_dldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-2";
+};
+
+&reg_dldo4 {
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vdd2v5-sata";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vdd1v2-sata";
+};
+
+&tcon_tv0 {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&ccu CLK_OUTA>;
+		clock-names = "lpo";
+		vbat-supply = <&reg_dldo2>;
+		vddio-supply = <&reg_dldo1>;
+		device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
+		/* TODO host wake line connected to PMIC GPIO pins */
+		shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
+		max-speed = <1500000>;
+	};
+};
+
 &usbphy {
 	usb1_vbus-supply = <&reg_vcc5v0>;
 	usb2_vbus-supply = <&reg_vcc5v0>;
diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index bd97ca3..06b6858 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -42,8 +42,10 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-r40-ccu.h>
 #include <dt-bindings/reset/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
 
 / {
 	#address-cells = <1>;
@@ -59,6 +61,7 @@
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
+			clock-accuracy = <50000>;
 			clock-output-names = "osc24M";
 		};
 
@@ -66,7 +69,8 @@
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
-			clock-output-names = "osc32k";
+			clock-accuracy = <20000>;
+			clock-output-names = "ext-osc32k";
 		};
 	};
 
@@ -99,12 +103,75 @@
 		};
 	};
 
+	de: display-engine {
+		compatible = "allwinner,sun8i-r40-display-engine";
+		allwinner,pipelines = <&mixer0>, <&mixer1>;
+		status = "disabled";
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
+		display_clocks: clock@1000000 {
+			compatible = "allwinner,sun8i-r40-de2-clk",
+				     "allwinner,sun8i-h3-de2-clk";
+			reg = <0x01000000 0x100000>;
+			clocks = <&ccu CLK_DE>,
+				 <&ccu CLK_BUS_DE>;
+			clock-names = "mod",
+				      "bus";
+			resets = <&ccu RST_BUS_DE>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		mixer0: mixer@1100000 {
+			compatible = "allwinner,sun8i-r40-de2-mixer-0";
+			reg = <0x01100000 0x100000>;
+			clocks = <&display_clocks CLK_BUS_MIXER0>,
+				 <&display_clocks CLK_MIXER0>;
+			clock-names = "bus",
+				      "mod";
+			resets = <&display_clocks RST_MIXER0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mixer0_out: port@1 {
+					reg = <1>;
+					mixer0_out_tcon_top: endpoint {
+						remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+					};
+				};
+			};
+		};
+
+		mixer1: mixer@1200000 {
+			compatible = "allwinner,sun8i-r40-de2-mixer-1";
+			reg = <0x01200000 0x100000>;
+			clocks = <&display_clocks CLK_BUS_MIXER1>,
+				 <&display_clocks CLK_MIXER1>;
+			clock-names = "bus",
+				      "mod";
+			resets = <&display_clocks RST_WB>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mixer1_out: port@1 {
+					reg = <1>;
+					mixer1_out_tcon_top: endpoint {
+						remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+					};
+				};
+			};
+		};
+
 		nmi_intc: interrupt-controller@1c00030 {
 			compatible = "allwinner,sun7i-a20-sc-nmi";
 			interrupt-controller;
@@ -248,23 +315,38 @@
 		ccu: clock@1c20000 {
 			compatible = "allwinner,sun8i-r40-ccu";
 			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&osc32k>;
+			clocks = <&osc24M>, <&rtc 0>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
 
+		rtc: rtc@1c20400 {
+			compatible = "allwinner,sun8i-r40-rtc",
+				     "allwinner,sun8i-h3-rtc";
+			reg = <0x01c20400 0x400>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+			clock-output-names = "osc32k", "osc32k-out";
+			clocks = <&osc32k>;
+			#clock-cells = <1>;
+		};
+
 		pio: pinctrl@1c20800 {
 			compatible = "allwinner,sun8i-r40-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
 			#gpio-cells = <3>;
 
+			clk_out_a_pin: clk-out-a-pin {
+				pins = "PI12";
+				function = "clk_out_a";
+			};
+
 			gmac_rgmii_pins: gmac-rgmii-pins {
 				pins = "PA0", "PA1", "PA2", "PA3",
 				       "PA4", "PA5", "PA6", "PA7",
@@ -312,6 +394,16 @@
 				pins = "PB22", "PB23";
 				function = "uart0";
 			};
+
+			uart3_pg_pins: uart3-pg-pins {
+				pins = "PG6", "PG7";
+				function = "uart3";
+			};
+
+			uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
+				pins = "PG8", "PG9";
+				function = "uart3";
+			};
 		};
 
 		wdt: watchdog@1c20c90 {
@@ -464,6 +556,19 @@
 			#size-cells = <0>;
 		};
 
+		ahci: sata@1c18000 {
+			compatible = "allwinner,sun8i-r40-ahci";
+			reg = <0x01c18000 0x1000>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
+			resets = <&ccu RST_BUS_SATA>;
+			resets-name = "ahci";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+		};
+
 		gmac: ethernet@1c50000 {
 			compatible = "allwinner,sun8i-r40-gmac";
 			syscon = <&ccu>;
@@ -474,8 +579,6 @@
 			reset-names = "stmmaceth";
 			clocks = <&ccu CLK_BUS_GMAC>;
 			clock-names = "stmmaceth";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 
 			gmac_mdio: mdio {
@@ -485,6 +588,213 @@
 			};
 		};
 
+		tcon_top: tcon-top@1c70000 {
+			compatible = "allwinner,sun8i-r40-tcon-top";
+			reg = <0x01c70000 0x1000>;
+			clocks = <&ccu CLK_BUS_TCON_TOP>,
+				 <&ccu CLK_TCON_TV0>,
+				 <&ccu CLK_TVE0>,
+				 <&ccu CLK_TCON_TV1>,
+				 <&ccu CLK_TVE1>,
+				 <&ccu CLK_DSI_DPHY>;
+			clock-names = "bus",
+				      "tcon-tv0",
+				      "tve0",
+				      "tcon-tv1",
+				      "tve1",
+				      "dsi";
+			clock-output-names = "tcon-top-tv0",
+					     "tcon-top-tv1",
+					     "tcon-top-dsi";
+			resets = <&ccu RST_BUS_TCON_TOP>;
+			#clock-cells = <1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_top_mixer0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					tcon_top_mixer0_in_mixer0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mixer0_out_tcon_top>;
+					};
+				};
+
+				tcon_top_mixer0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+						reg = <0>;
+					};
+
+					tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
+						reg = <1>;
+					};
+
+					tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+					};
+
+					tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
+						reg = <3>;
+						remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
+					};
+				};
+
+				tcon_top_mixer1_in: port@2 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <2>;
+
+					tcon_top_mixer1_in_mixer1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&mixer1_out_tcon_top>;
+					};
+				};
+
+				tcon_top_mixer1_out: port@3 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <3>;
+
+					tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+						reg = <0>;
+					};
+
+					tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
+						reg = <1>;
+					};
+
+					tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+					};
+
+					tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
+						reg = <3>;
+						remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
+					};
+				};
+
+				tcon_top_hdmi_in: port@4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <4>;
+
+					tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_tv0_out_tcon_top>;
+					};
+
+					tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_tv1_out_tcon_top>;
+					};
+				};
+
+				tcon_top_hdmi_out: port@5 {
+					reg = <5>;
+
+					tcon_top_hdmi_out_hdmi: endpoint {
+						remote-endpoint = <&hdmi_in_tcon_top>;
+					};
+				};
+			};
+		};
+
+		tcon_tv0: lcd-controller@1c73000 {
+			compatible = "allwinner,sun8i-r40-tcon-tv";
+			reg = <0x01c73000 0x1000>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
+			clock-names = "ahb", "tcon-ch1";
+			resets = <&ccu RST_BUS_TCON_TV0>;
+			reset-names = "lcd";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_tv0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+					};
+
+					tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+					};
+				};
+
+				tcon_tv0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon_tv0_out_tcon_top: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+					};
+				};
+			};
+		};
+
+		tcon_tv1: lcd-controller@1c74000 {
+			compatible = "allwinner,sun8i-r40-tcon-tv";
+			reg = <0x01c74000 0x1000>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
+			clock-names = "ahb", "tcon-ch1";
+			resets = <&ccu RST_BUS_TCON_TV1>;
+			reset-names = "lcd";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_tv1_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
+					};
+
+					tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
+					};
+				};
+
+				tcon_tv1_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon_tv1_out_tcon_top: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
+					};
+				};
+			};
+		};
+
 		gic: interrupt-controller@1c81000 {
 			compatible = "arm,gic-400";
 			reg = <0x01c81000 0x1000>,
@@ -495,6 +805,50 @@
 			#interrupt-cells = <3>;
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
+
+		hdmi: hdmi@1ee0000 {
+			compatible = "allwinner,sun8i-r40-dw-hdmi",
+				     "allwinner,sun8i-a83t-dw-hdmi";
+			reg = <0x01ee0000 0x10000>;
+			reg-io-width = <1>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
+				 <&ccu CLK_HDMI>;
+			clock-names = "iahb", "isfr", "tmds";
+			resets = <&ccu RST_BUS_HDMI1>;
+			reset-names = "ctrl";
+			phys = <&hdmi_phy>;
+			phy-names = "hdmi-phy";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				hdmi_in: port@0 {
+					reg = <0>;
+
+					hdmi_in_tcon_top: endpoint {
+						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
+					};
+				};
+
+				hdmi_out: port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		hdmi_phy: hdmi-phy@1ef0000 {
+			compatible = "allwinner,sun8i-r40-hdmi-phy";
+			reg = <0x01ef0000 0x10000>;
+			clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
+				 <&ccu 7>, <&ccu 16>;
+			clock-names = "bus", "mod", "pll-0", "pll-1";
+			resets = <&ccu RST_BUS_HDMI0>;
+			reset-names = "phy";
+			#phy-cells = <0>;
+		};
 	};
 
 	timer {
diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
index 35859d8..54ad4db 100644
--- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -87,6 +87,12 @@
 	};
 };
 
+&ahci {
+	phy-supply = <&reg_eldo3>;	/* VDD12-SATA */
+	ahci-supply = <&reg_dldo4>;	/* VDD25-SATA */
+	status = "okay";
+};
+
 &ehci1 {
 	/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
 	status = "okay";
@@ -95,7 +101,7 @@
 &i2c0 {
 	status = "okay";
 
-	axp22x: pmic@68 {
+	axp22x: pmic@34 {
 		compatible = "x-powers,axp221";
 		reg = <0x34>;
 		interrupt-parent = <&nmi_intc>;
@@ -152,6 +158,18 @@
 	regulator-name = "vcc-wifi";
 };
 
+&reg_dldo4 {
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vdd2v5-sata";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vdd1v2-sata";
+};
+
 &mmc0 {
 	vmmc-supply = <&reg_dcdc1>;
 	bus-width = <4>;
diff --git a/arch/arm/dts/sunxi-itead-core-common.dtsi b/arch/arm/dts/sunxi-itead-core-common.dtsi
index 2565d51..0d002f8 100644
--- a/arch/arm/dts/sunxi-itead-core-common.dtsi
+++ b/arch/arm/dts/sunxi-itead-core-common.dtsi
@@ -65,8 +65,6 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
 
 	axp209: pmic@34 {
@@ -75,8 +73,6 @@
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
 	status = "okay";
 };
 
@@ -125,7 +121,7 @@
 
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 31ba52b..a3cd475 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -33,7 +33,7 @@
 
 		cpu0: cpu@0 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0 0x000>;
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
@@ -42,7 +42,7 @@
 
 		cpu1: cpu@1 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0 0x001>;
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index b9ed613..baf2326 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -43,7 +43,7 @@
 
 		cpu0: cpu@0 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
+			compatible = "arm,cortex-a72";
 			reg = <0 0x000>;
 			clocks = <&sys_clk 32>;
 			enable-method = "psci";
@@ -53,7 +53,7 @@
 
 		cpu1: cpu@1 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
+			compatible = "arm,cortex-a72";
 			reg = <0 0x001>;
 			clocks = <&sys_clk 32>;
 			enable-method = "psci";
@@ -63,7 +63,7 @@
 
 		cpu2: cpu@100 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0 0x100>;
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
@@ -73,7 +73,7 @@
 
 		cpu3: cpu@101 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0 0x101>;
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
@@ -206,13 +206,10 @@
 			cooling-maps {
 				map0 {
 					trip = <&cpu_alert>;
-					cooling-device = <&cpu0
-					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-				map1 {
-					trip = <&cpu_alert>;
-					cooling-device = <&cpu2
-					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
@@ -891,6 +888,53 @@
 			};
 		};
 
+		pcie: pcie@66000000 {
+			compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+			status = "disabled";
+			reg-names = "dbi", "link", "config";
+			reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
+			      <0x2fff0000 0x10000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			clocks = <&sys_clk 24>;
+			resets = <&sys_rst 24>;
+			num-lanes = <1>;
+			num-viewport = <1>;
+			bus-range = <0x0 0xff>;
+			device_type = "pci";
+			ranges =
+			/* downstream I/O */
+				<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
+			/* non-prefetchable memory */
+				<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
+			#interrupt-cells = <1>;
+			interrupt-names = "dma", "msi";
+			interrupts = <0 224 4>, <0 225 4>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc 0>,	/* INTA */
+					<0 0 0 2 &pcie_intc 1>,	/* INTB */
+					<0 0 0 3 &pcie_intc 2>,	/* INTC */
+					<0 0 0 4 &pcie_intc 3>;	/* INTD */
+			phy-names = "pcie-phy";
+			phys = <&pcie_phy>;
+
+			pcie_intc: legacy-interrupt-controller {
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <0 226 4>;
+			};
+		};
+
+		pcie_phy: phy@66038000 {
+			compatible = "socionext,uniphier-ld20-pcie-phy";
+			reg = <0x66038000 0x4000>;
+			#phy-cells = <0>;
+			clocks = <&sys_clk 24>;
+			resets = <&sys_rst 24>;
+			socionext,syscon = <&soc_glue>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5b";
 			status = "disabled";
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index b73d594..c2706ce 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -235,6 +235,16 @@
 			};
 		};
 
+		dmac: dma-controller@5a000000 {
+			compatible = "socionext,uniphier-mio-dmac";
+			reg = <0x5a000000 0x1000>;
+			interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+				     <0 71 4>, <0 72 4>, <0 73 4>;
+			clocks = <&mio_clk 7>;
+			resets = <&mio_rst 7>;
+			#dma-cells = <1>;
+		};
+
 		sd: sdhc@5a400000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
@@ -246,6 +256,8 @@
 			clocks = <&mio_clk 0>;
 			reset-names = "host", "bridge";
 			resets = <&mio_rst 0>, <&mio_rst 3>;
+			dma-names = "rx-tx";
+			dmas = <&dmac 4>;
 			bus-width = <4>;
 			cap-sd-highspeed;
 			sd-uhs-sdr12;
@@ -263,6 +275,8 @@
 			clocks = <&mio_clk 1>;
 			reset-names = "host", "bridge", "hw";
 			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+			dma-names = "rx-tx";
+			dmas = <&dmac 6>;
 			bus-width = <8>;
 			cap-mmc-highspeed;
 			cap-mmc-hw-reset;
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index ef34208..d090fc7 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -269,6 +269,16 @@
 			};
 		};
 
+		dmac: dma-controller@5a000000 {
+			compatible = "socionext,uniphier-mio-dmac";
+			reg = <0x5a000000 0x1000>;
+			interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+				     <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+			clocks = <&mio_clk 7>;
+			resets = <&mio_rst 7>;
+			#dma-cells = <1>;
+		};
+
 		sd: sdhc@5a400000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
@@ -280,6 +290,8 @@
 			clocks = <&mio_clk 0>;
 			reset-names = "host", "bridge";
 			resets = <&mio_rst 0>, <&mio_rst 3>;
+			dma-names = "rx-tx";
+			dmas = <&dmac 4>;
 			bus-width = <4>;
 			cap-sd-highspeed;
 			sd-uhs-sdr12;
@@ -297,6 +309,8 @@
 			clocks = <&mio_clk 1>;
 			reset-names = "host", "bridge", "hw";
 			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+			dma-names = "rx-tx";
+			dmas = <&dmac 5>;
 			bus-width = <8>;
 			cap-mmc-highspeed;
 			cap-mmc-hw-reset;
@@ -313,6 +327,8 @@
 			clocks = <&mio_clk 2>;
 			reset-names = "host", "bridge";
 			resets = <&mio_rst 2>, <&mio_rst 5>;
+			dma-names = "rx-tx";
+			dmas = <&dmac 6>;
 			bus-width = <4>;
 			cap-sd-highspeed;
 		};
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index fa25ffd..4e11e85 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -141,8 +141,10 @@
 			cooling-maps {
 				map {
 					trip = <&cpu_alert>;
-					cooling-device = <&cpu0
-					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts
index 4fb12b8..1965e4d 100644
--- a/arch/arm/dts/uniphier-pxs3-ref.dts
+++ b/arch/arm/dts/uniphier-pxs3-ref.dts
@@ -109,6 +109,10 @@
 	status = "okay";
 };
 
+&pcie {
+	status = "okay";
+};
+
 &nand {
 	status = "okay";
 };
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index f629c6a..961d4d3 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -39,7 +39,7 @@
 
 		cpu0: cpu@0 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0 0x000>;
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
@@ -48,7 +48,7 @@
 
 		cpu1: cpu@1 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0 0x001>;
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
@@ -57,7 +57,7 @@
 
 		cpu2: cpu@2 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0 0x002>;
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
@@ -66,7 +66,7 @@
 
 		cpu3: cpu@3 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0 0x003>;
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
@@ -765,6 +765,53 @@
 			};
 		};
 
+		pcie: pcie@66000000 {
+			compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+			status = "disabled";
+			reg-names = "dbi", "link", "config";
+			reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
+			      <0x2fff0000 0x10000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			clocks = <&sys_clk 24>;
+			resets = <&sys_rst 24>;
+			num-lanes = <1>;
+			num-viewport = <1>;
+			bus-range = <0x0 0xff>;
+			device_type = "pci";
+			ranges =
+			/* downstream I/O */
+				<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
+			/* non-prefetchable memory */
+				<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
+			#interrupt-cells = <1>;
+			interrupt-names = "dma", "msi";
+			interrupts = <0 224 4>, <0 225 4>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc 0>,	/* INTA */
+					<0 0 0 2 &pcie_intc 1>,	/* INTB */
+					<0 0 0 3 &pcie_intc 2>,	/* INTC */
+					<0 0 0 4 &pcie_intc 3>;	/* INTD */
+			phy-names = "pcie-phy";
+			phys = <&pcie_phy>;
+
+			pcie_intc: legacy-interrupt-controller {
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <0 226 4>;
+			};
+		};
+
+		pcie_phy: phy@66038000 {
+			compatible = "socionext,uniphier-pxs3-pcie-phy";
+			reg = <0x66038000 0x4000>;
+			#phy-cells = <0>;
+			clocks = <&sys_clk 24>;
+			resets = <&sys_rst 24>;
+			socionext,syscon = <&soc_glue>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5b";
 			status = "disabled";
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index f7fcf6b..efce027 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -239,6 +239,16 @@
 			};
 		};
 
+		dmac: dma-controller@5a000000 {
+			compatible = "socionext,uniphier-mio-dmac";
+			reg = <0x5a000000 0x1000>;
+			interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+				     <0 71 4>, <0 72 4>, <0 73 4>;
+			clocks = <&mio_clk 7>;
+			resets = <&mio_rst 7>;
+			#dma-cells = <1>;
+		};
+
 		sd: sdhc@5a400000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
@@ -250,6 +260,8 @@
 			clocks = <&mio_clk 0>;
 			reset-names = "host", "bridge";
 			resets = <&mio_rst 0>, <&mio_rst 3>;
+			dma-names = "rx-tx";
+			dmas = <&dmac 4>;
 			bus-width = <4>;
 			cap-sd-highspeed;
 			sd-uhs-sdr12;
@@ -267,6 +279,8 @@
 			clocks = <&mio_clk 1>;
 			reset-names = "host", "bridge", "hw";
 			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+			dma-names = "rx-tx";
+			dmas = <&dmac 6>;
 			bus-width = <8>;
 			cap-mmc-highspeed;
 			cap-mmc-hw-reset;
diff --git a/arch/arm/dts/vf-colibri-u-boot.dtsi b/arch/arm/dts/vf-colibri-u-boot.dtsi
new file mode 100644
index 0000000..db86739
--- /dev/null
+++ b/arch/arm/dts/vf-colibri-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&aips0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ddr {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
index 923dc24..5ce1707 100644
--- a/arch/arm/dts/vf-colibri.dtsi
+++ b/arch/arm/dts/vf-colibri.dtsi
@@ -1,18 +1,37 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2014 Toradex AG
+ * Copyright 2014-2019 Toradex AG
  */
+
+/dts-v1/;
 #include "vf.dtsi"
+#include "vf610-pinfunc.h"
 
 / {
 	chosen {
 		stdout-path = &uart0;
 	};
+
+	aliases {
+		usb0 = &ehci0; /* required for ums */
+	};
+
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh1_reg>;
+		regulator-name = "VCC_USB[1-4]";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN */
+	};
 };
 
 &dspi1 {
-	status = "okay";
 	bus-num = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dspi1>;
+	status = "okay";
 
 	spi_cmd: sspi@0 {
 		reg = <0>;
@@ -29,8 +48,183 @@
 &ehci1 {
 	dr_mode = "host";
 	status = "okay";
+	vbus-supply = <&reg_usbh_vbus>;
+};
+
+&esdhc1 {
+	bus-width = <4>;
+	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc1>;
+	status = "okay";
+};
+
+&fec1 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
+	status = "okay";
+
+	/* M41T0M6 real time clock on carrier board */
+	rtc: m41t0m6@68 {
+		compatible = "st,m41t0";
+		reg = <0x68>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ddr>;
+
+	pinctrl_ddr: ddrgrp {
+		fsl,pins = <
+			VF610_PAD_DDR_A15__DDR_A_15             0x180
+			VF610_PAD_DDR_A14__DDR_A_14             0x180
+			VF610_PAD_DDR_A13__DDR_A_13             0x180
+			VF610_PAD_DDR_A12__DDR_A_12             0x180
+			VF610_PAD_DDR_A11__DDR_A_11             0x180
+			VF610_PAD_DDR_A10__DDR_A_10             0x180
+			VF610_PAD_DDR_A9__DDR_A_9               0x180
+			VF610_PAD_DDR_A8__DDR_A_8               0x180
+			VF610_PAD_DDR_A7__DDR_A_7               0x180
+			VF610_PAD_DDR_A6__DDR_A_6               0x180
+			VF610_PAD_DDR_A5__DDR_A_5               0x180
+			VF610_PAD_DDR_A4__DDR_A_4               0x180
+			VF610_PAD_DDR_A3__DDR_A_3               0x180
+			VF610_PAD_DDR_A2__DDR_A_2               0x180
+			VF610_PAD_DDR_A1__DDR_A_1               0x180
+			VF610_PAD_DDR_A0__DDR_A_0               0x180
+			VF610_PAD_DDR_BA2__DDR_BA_2             0x180
+			VF610_PAD_DDR_BA1__DDR_BA_1             0x180
+			VF610_PAD_DDR_BA0__DDR_BA_0             0x180
+			VF610_PAD_DDR_CAS__DDR_CAS_B            0x180
+			VF610_PAD_DDR_CKE__DDR_CKE_0            0x180
+			VF610_PAD_DDR_CLK__DDR_CLK_0            0x180
+			VF610_PAD_DDR_CS__DDR_CS_B_0            0x180
+			VF610_PAD_DDR_D15__DDR_D_15             0x10180
+			VF610_PAD_DDR_D14__DDR_D_14             0x10180
+			VF610_PAD_DDR_D13__DDR_D_13             0x10180
+			VF610_PAD_DDR_D12__DDR_D_12             0x10180
+			VF610_PAD_DDR_D11__DDR_D_11             0x10180
+			VF610_PAD_DDR_D10__DDR_D_10             0x10180
+			VF610_PAD_DDR_D9__DDR_D_9               0x10180
+			VF610_PAD_DDR_D8__DDR_D_8               0x10180
+			VF610_PAD_DDR_D7__DDR_D_7               0x10180
+			VF610_PAD_DDR_D6__DDR_D_6               0x10180
+			VF610_PAD_DDR_D5__DDR_D_5               0x10180
+			VF610_PAD_DDR_D4__DDR_D_4               0x10180
+			VF610_PAD_DDR_D3__DDR_D_3               0x10180
+			VF610_PAD_DDR_D2__DDR_D_2               0x10180
+			VF610_PAD_DDR_D1__DDR_D_1               0x10180
+			VF610_PAD_DDR_D0__DDR_D_0               0x10180
+			VF610_PAD_DDR_DQM1__DDR_DQM_1           0x10180
+			VF610_PAD_DDR_DQM0__DDR_DQM_0           0x10180
+			VF610_PAD_DDR_DQS1__DDR_DQS_1           0x10180
+			VF610_PAD_DDR_DQS0__DDR_DQS_0           0x10180
+			VF610_PAD_DDR_RAS__DDR_RAS_B            0x180
+			VF610_PAD_DDR_WE__DDR_WE_B              0x180
+			VF610_PAD_DDR_ODT1__DDR_ODT_0           0x180
+			VF610_PAD_DDR_ODT0__DDR_ODT_1           0x180
+			VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1    0x180
+			VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2    0x180
+			VF610_PAD_DDR_RESETB                    0x180
+		>;
+	};
+
+	pinctrl_dspi1: dspi1grp {
+		fsl,pins = <
+			VF610_PAD_PTD5__DSPI1_CS0		0x33e2
+			VF610_PAD_PTD6__DSPI1_SIN		0x33e1
+			VF610_PAD_PTD7__DSPI1_SOUT		0x33e2
+			VF610_PAD_PTD8__DSPI1_SCK		0x33e2
+		>;
+	};
+
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
+			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
+			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
+			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
+			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
+			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
+			VF610_PAD_PTB20__GPIO_42		0x219d
+		>;
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			VF610_PAD_PTA6__RMII_CLKOUT		0x30df
+			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30df
+			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30df
+			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30df
+			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30df
+			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30df
+			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30df
+			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30df
+			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30df
+			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30df
+		>;
+	};
+
+	pinctrl_i2c0: i2c0grp {
+		fsl,pins = <
+			VF610_PAD_PTB14__I2C0_SCL		0x37ff
+			VF610_PAD_PTB15__I2C0_SDA		0x37ff
+		>;
+	};
+
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			VF610_PAD_PTD23__NF_IO7			0x28df
+			VF610_PAD_PTD22__NF_IO6			0x28df
+			VF610_PAD_PTD21__NF_IO5			0x28df
+			VF610_PAD_PTD20__NF_IO4			0x28df
+			VF610_PAD_PTD19__NF_IO3			0x28df
+			VF610_PAD_PTD18__NF_IO2			0x28df
+			VF610_PAD_PTD17__NF_IO1			0x28df
+			VF610_PAD_PTD16__NF_IO0			0x28df
+			VF610_PAD_PTB24__NF_WE_B		0x28c2
+			VF610_PAD_PTB25__NF_CE0_B		0x28c2
+			VF610_PAD_PTB27__NF_RE_B		0x28c2
+			VF610_PAD_PTC26__NF_RB_B		0x283d
+			VF610_PAD_PTC27__NF_ALE			0x28c2
+			VF610_PAD_PTC28__NF_CLE			0x28c2
+		>;
+	};
+
+	pinctrl_uart0: uart0grp {
+		fsl,pins = <
+			VF610_PAD_PTB10__UART0_TX		0x11af
+			VF610_PAD_PTB11__UART0_RX		0x11af
+			VF610_PAD_PTB12__UART0_RTS		0x11af
+			VF610_PAD_PTB13__UART0_CTS		0x11af
+		>;
+	};
+
+	pinctrl_usbh1_reg: gpio_usb_vbus {
+		fsl,pins = <
+			VF610_PAD_PTD4__GPIO_83			0x22ed
+		>;
+	};
+};
+
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_nfc>;
+	status = "okay";
 };
 
 &uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index ad30059..5e3b2c5 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -22,6 +22,10 @@
 		spi1 = &dspi1;
 		ehci0 = &ehci0;
 		ehci1 = &ehci1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
 	};
 
 	soc {
@@ -89,6 +93,22 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c@40066000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x40066000 0x1000>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@40067000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x40067000 0x1000>;
+				status = "disabled";
+			};
+
 			iomuxc: iomuxc@40048000 {
 				compatible = "fsl,vf610-iomuxc";
 				reg = <0x40048000 0x1000>;
@@ -156,6 +176,48 @@
 				reg = <0x400b4000 0x800>;
 				status = "disabled";
 			};
+
+			esdhc1: esdhc@400b2000 {
+				compatible = "fsl,esdhc";
+				reg = <0x400b2000 0x1000>;
+				status = "disabled";
+			};
+
+			fec0: fec@400d0000 {
+			      compatible = "fsl,mvf600-fec";
+			      reg = <0x400d0000 0x1000>;
+			      status = "disabled";
+			};
+
+			fec1: fec@400d1000 {
+			      compatible = "fsl,mvf600-fec";
+			      reg = <0x400d1000 0x1000>;
+			      status = "disabled";
+			};
+
+			nfc: nand@400e0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-nfc";
+				reg = <0x400e0000 0x4000>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@400e6000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x400e6000 0x1000>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@400e7000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,vf610-i2c";
+				reg = <0x400e7000 0x1000>;
+				status = "disabled";
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/vf500-colibri.dts b/arch/arm/dts/vf500-colibri.dts
index 3f33d97..c83a16f 100644
--- a/arch/arm/dts/vf500-colibri.dts
+++ b/arch/arm/dts/vf500-colibri.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "vf-colibri.dtsi"
+#include "vf-colibri-u-boot.dtsi"
 
 / {
 	model = "Toradex Colibri VF50";
diff --git a/arch/arm/dts/vf610-bk4r1-u-boot.dtsi b/arch/arm/dts/vf610-bk4r1-u-boot.dtsi
new file mode 100644
index 0000000..088926b
--- /dev/null
+++ b/arch/arm/dts/vf610-bk4r1-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&aips0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ddr {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/vf610-bk4r1.dts b/arch/arm/dts/vf610-bk4r1.dts
new file mode 100644
index 0000000..55cd533
--- /dev/null
+++ b/arch/arm/dts/vf610-bk4r1.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * (C) Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+ *
+ * Copyright 2016 Toradex AG
+ */
+
+/dts-v1/;
+#include "vf610-pcm052.dtsi"
+#include "vf610-pinfunc.h"
+
+/ {
+	model = "Liebherr (LVF) BK4 Vybrid Board";
+	compatible = "lvf,bk4", "fsl,vf610";
+
+	leds {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		compatible = "gpio-leds";
+
+		/* PTE15 PORT3[24] H6 green */
+		led@0 {
+			label = "0";
+			gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTA12 PORT0[5] H5 green */
+		led@1 {
+			label = "1";
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTE20 PORT3[39] H4 green */
+		led@2 {
+			label = "2";
+			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTE12 PORT3[21] H3 green */
+		led@3 {
+			label = "3";
+			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* LED6 is now PRESET ETH -> PTA16 PORT0[6]  H6 red */
+		/* PTE9  PORT3[18] H5 red */
+		led@4 {
+			label = "5";
+			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTE23 PORT4[0]  H4 red */
+		led@5 {
+			label = "6";
+			gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* PTE16 PORT3[25] H3 red */
+		led@6 {
+			label = "7";
+			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-0 = <&pinctrl_ddr &pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			/* ETH control pins */
+			VF610_PAD_PTE17__GPIO_122		0x1183
+			VF610_PAD_PTA16__GPIO_6	0x1183
+		>;
+	};
+
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <
+			/* LEDS */
+			VF610_PAD_PTE15__GPIO_120	0x1183
+			VF610_PAD_PTA12__GPIO_5	0x1183
+			VF610_PAD_PTE9__GPIO_114	0x1183
+			VF610_PAD_PTE20__GPIO_125	0x1183
+			VF610_PAD_PTE23__GPIO_128	0x1183
+			VF610_PAD_PTE16__GPIO_121	0x1183
+		>;
+	};
+};
diff --git a/arch/arm/dts/vf610-colibri.dts b/arch/arm/dts/vf610-colibri.dts
index 0a6b937..7275fec 100644
--- a/arch/arm/dts/vf610-colibri.dts
+++ b/arch/arm/dts/vf610-colibri.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "vf-colibri.dtsi"
+#include "vf-colibri-u-boot.dtsi"
 
 / {
 	model = "Toradex Colibri VF61";
diff --git a/arch/arm/dts/pcm052.dts b/arch/arm/dts/vf610-pcm052.dts
similarity index 81%
rename from arch/arm/dts/pcm052.dts
rename to arch/arm/dts/vf610-pcm052.dts
index 6489fdc..2202602 100644
--- a/arch/arm/dts/pcm052.dts
+++ b/arch/arm/dts/vf610-pcm052.dts
@@ -4,7 +4,7 @@
  */
 
 /dts-v1/;
-#include "vf.dtsi"
+#include "vf610-pcm052.dtsi"
 
 / {
 	model = "Phytec phyCORE-Vybrid";
@@ -15,7 +15,3 @@
 	};
 
 };
-
-&uart1 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/vf610-pcm052.dtsi b/arch/arm/dts/vf610-pcm052.dtsi
new file mode 100644
index 0000000..1383d03
--- /dev/null
+++ b/arch/arm/dts/vf610-pcm052.dtsi
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * (C) Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+ *
+ */
+
+/dts-v1/;
+#include "vf.dtsi"
+#include "vf610-pinfunc.h"
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	aliases {
+		spi0 = &qspi0;
+		mmc0 = &esdhc1;
+	};
+};
+
+&esdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc1>;
+	bus-width = <4>;
+	cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&fec0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eth>;
+
+	phy-mode = "rmii";
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eth1>;
+
+	phy-mode = "rmii";
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	eeprom: eeprom@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+		pagesize = <64>;
+		u-boot,i2c-offset-len = <2>;
+	};
+
+	m41t62: rtc@68 {
+		compatible = "st,m41t62";
+		reg = <0x68>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ddr>;
+
+	pinctrl_ddr: ddrgrp {
+		fsl,pins = <
+			VF610_PAD_DDR_A15__DDR_A_15             0x1c0
+			VF610_PAD_DDR_A14__DDR_A_14             0x1c0
+			VF610_PAD_DDR_A13__DDR_A_13             0x1c0
+			VF610_PAD_DDR_A12__DDR_A_12             0x1c0
+			VF610_PAD_DDR_A11__DDR_A_11             0x1c0
+			VF610_PAD_DDR_A10__DDR_A_10             0x1c0
+			VF610_PAD_DDR_A9__DDR_A_9               0x1c0
+			VF610_PAD_DDR_A8__DDR_A_8               0x1c0
+			VF610_PAD_DDR_A7__DDR_A_7               0x1c0
+			VF610_PAD_DDR_A6__DDR_A_6               0x1c0
+			VF610_PAD_DDR_A5__DDR_A_5               0x1c0
+			VF610_PAD_DDR_A4__DDR_A_4               0x1c0
+			VF610_PAD_DDR_A3__DDR_A_3               0x1c0
+			VF610_PAD_DDR_A2__DDR_A_2               0x1c0
+			VF610_PAD_DDR_A1__DDR_A_1               0x1c0
+			VF610_PAD_DDR_A0__DDR_A_0               0x1c0
+			VF610_PAD_DDR_BA2__DDR_BA_2             0x1c0
+			VF610_PAD_DDR_BA1__DDR_BA_1             0x1c0
+			VF610_PAD_DDR_BA0__DDR_BA_0             0x1c0
+			VF610_PAD_DDR_CAS__DDR_CAS_B            0x1c0
+			VF610_PAD_DDR_CKE__DDR_CKE_0            0x1c0
+			VF610_PAD_DDR_CLK__DDR_CLK_0            0x101c0
+			VF610_PAD_DDR_CS__DDR_CS_B_0            0x1c0
+			VF610_PAD_DDR_D15__DDR_D_15             0x1c0
+			VF610_PAD_DDR_D14__DDR_D_14             0x1c0
+			VF610_PAD_DDR_D13__DDR_D_13             0x1c0
+			VF610_PAD_DDR_D12__DDR_D_12             0x1c0
+			VF610_PAD_DDR_D11__DDR_D_11             0x1c0
+			VF610_PAD_DDR_D10__DDR_D_10             0x1c0
+			VF610_PAD_DDR_D9__DDR_D_9               0x1c0
+			VF610_PAD_DDR_D8__DDR_D_8               0x1c0
+			VF610_PAD_DDR_D7__DDR_D_7               0x1c0
+			VF610_PAD_DDR_D6__DDR_D_6               0x1c0
+			VF610_PAD_DDR_D5__DDR_D_5               0x1c0
+			VF610_PAD_DDR_D4__DDR_D_4               0x1c0
+			VF610_PAD_DDR_D3__DDR_D_3               0x1c0
+			VF610_PAD_DDR_D2__DDR_D_2               0x1c0
+			VF610_PAD_DDR_D1__DDR_D_1               0x1c0
+			VF610_PAD_DDR_D0__DDR_D_0               0x1c0
+			VF610_PAD_DDR_DQM1__DDR_DQM_1           0x1c0
+			VF610_PAD_DDR_DQM0__DDR_DQM_0           0x1c0
+			VF610_PAD_DDR_DQS1__DDR_DQS_1           0x101c0
+			VF610_PAD_DDR_DQS0__DDR_DQS_0           0x101c0
+			VF610_PAD_DDR_RAS__DDR_RAS_B            0x1c0
+			VF610_PAD_DDR_WE__DDR_WE_B              0x1c0
+			VF610_PAD_DDR_ODT1__DDR_ODT_0           0x1c0
+			VF610_PAD_DDR_ODT0__DDR_ODT_1           0x1c0
+			VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1    0x1c0
+			VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2    0x1c0
+			VF610_PAD_DDR_RESETB                    0x1006c
+		>;
+	};
+
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
+			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
+			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
+			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
+			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
+			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
+			VF610_PAD_PTB28__GPIO_98		0x219d
+		>;
+	};
+
+	pinctrl_eth: ethgrp {
+		fsl,pins = <
+			VF610_PAD_PTA6__RMII_CLKIN              0x30dd
+			VF610_PAD_PTC0__ENET_RMII0_MDC          0x30de
+			VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
+			VF610_PAD_PTC2__ENET_RMII0_CRS          0x30dd
+			VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
+			VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
+			VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
+			VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
+			VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
+			VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
+		>;
+	};
+
+	pinctrl_eth1: eth1grp {
+		fsl,pins = <
+			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30de
+			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30df
+			VF610_PAD_PTC11__ENET_RMII1_CRS	0x30dd
+			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30dd
+			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30dd
+			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30dd
+			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30de
+			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30de
+			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30de
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			VF610_PAD_PTA22__I2C2_SCL		0x34df
+			VF610_PAD_PTA23__I2C2_SDA		0x34df
+		>;
+	};
+
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			VF610_PAD_PTD31__NF_IO15		0x28df
+			VF610_PAD_PTD30__NF_IO14		0x28df
+			VF610_PAD_PTD29__NF_IO13		0x28df
+			VF610_PAD_PTD28__NF_IO12		0x28df
+			VF610_PAD_PTD27__NF_IO11		0x28df
+			VF610_PAD_PTD26__NF_IO10		0x28df
+			VF610_PAD_PTD25__NF_IO9		0x28df
+			VF610_PAD_PTD24__NF_IO8		0x28df
+			VF610_PAD_PTD23__NF_IO7		0x28df
+			VF610_PAD_PTD22__NF_IO6		0x28df
+			VF610_PAD_PTD21__NF_IO5		0x28df
+			VF610_PAD_PTD20__NF_IO4		0x28df
+			VF610_PAD_PTD19__NF_IO3		0x28df
+			VF610_PAD_PTD18__NF_IO2		0x28df
+			VF610_PAD_PTD17__NF_IO1		0x28df
+			VF610_PAD_PTD16__NF_IO0		0x28df
+			VF610_PAD_PTB24__NF_WE_B		0x28c2
+			VF610_PAD_PTB25__NF_CE0_B		0x28c2
+			VF610_PAD_PTB27__NF_RE_B		0x28c2
+			VF610_PAD_PTC26__NF_RB_B		0x283d
+			VF610_PAD_PTC27__NF_ALE		0x28c2
+			VF610_PAD_PTC28__NF_CLE		0x28c2
+		>;
+	};
+
+	pinctrl_qspi0: qspi0grp {
+		fsl,pins = <
+			VF610_PAD_PTD0__QSPI0_A_QSCK	0x397f
+			VF610_PAD_PTD1__QSPI0_A_CS0	0x397f
+			VF610_PAD_PTD2__QSPI0_A_DATA3	0x397f
+			VF610_PAD_PTD3__QSPI0_A_DATA2	0x397f
+			VF610_PAD_PTD4__QSPI0_A_DATA1	0x397f
+			VF610_PAD_PTD5__QSPI0_A_DATA0	0x397f
+			VF610_PAD_PTD7__QSPI0_B_QSCK	0x397f
+			VF610_PAD_PTD8__QSPI0_B_CS0	0x397f
+			VF610_PAD_PTD11__QSPI0_B_DATA1	0x397f
+			VF610_PAD_PTD12__QSPI0_B_DATA0	0x397f
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			VF610_PAD_PTB4__UART1_TX                0x21a2
+			VF610_PAD_PTB5__UART1_RX                0x21a1
+		>;
+	};
+};
+
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_nfc>;
+
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+
+	status = "okay";
+};
+
+&qspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi0>;
+
+	bus-num = <0>;
+	num-cs = <2>;
+	status = "okay";
+
+	qflash0: spi_flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <108000000>;
+		reg = <0>;
+	};
+
+	qflash1: spi_flash@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <66000000>;
+		reg = <1>;
+	};
+};
diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h
index fcad713..9456719 100644
--- a/arch/arm/dts/vf610-pinfunc.h
+++ b/arch/arm/dts/vf610-pinfunc.h
@@ -807,4 +807,54 @@
 #define VF610_PAD_PTA7__GPIO_134		0x218 0x000 ALT0 0x0
 #define VF610_PAD_PTA7__VIU_PIX_CLK		0x218 0x3AC ALT1 0x1
 
+#define VF610_PAD_DDR_RESETB			0x21c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A15__DDR_A_15		0x220 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A14__DDR_A_14		0x224 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A13__DDR_A_13		0x228 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A12__DDR_A_12		0x22c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A11__DDR_A_11		0x230 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A10__DDR_A_10		0x234 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A9__DDR_A_9		0x238 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A8__DDR_A_8		0x23c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A7__DDR_A_7		0x240 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A6__DDR_A_6		0x244 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A5__DDR_A_5		0x248 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A4__DDR_A_4		0x24c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A3__DDR_A_3		0x250 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A2__DDR_A_2		0x254 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A1__DDR_A_1		0x258 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A0__DDR_A_0		0x25c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA2__DDR_BA_2		0x260 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA1__DDR_BA_1		0x264 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA0__DDR_BA_0		0x268 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CAS__DDR_CAS_B		0x26c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CKE__DDR_CKE_0		0x270 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CLK__DDR_CLK_0		0x274 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CS__DDR_CS_B_0		0x278 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D15__DDR_D_15		0x27c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D14__DDR_D_14		0x280 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D13__DDR_D_13		0x284 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D12__DDR_D_12		0x288 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D11__DDR_D_11		0x28c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D10__DDR_D_10		0x290 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D9__DDR_D_9		0x294 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D8__DDR_D_8		0x298 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D7__DDR_D_7		0x29c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D6__DDR_D_6		0x2a0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D5__DDR_D_5		0x2a4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D4__DDR_D_4		0x2a8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D3__DDR_D_3		0x2ac 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D2__DDR_D_2		0x2b0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D1__DDR_D_1		0x2b4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D0__DDR_D_0		0x2b8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM1__DDR_DQM_1		0x2bc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM0__DDR_DQM_0		0x2c0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS1__DDR_DQS_1		0x2c4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS0__DDR_DQS_0		0x2c8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_RAS__DDR_RAS_B		0x2cc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_WE__DDR_WE_B		0x2d0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT1__DDR_ODT_0		0x2d4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT0__DDR_ODT_1		0x2d8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	0x2dc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2	0x2e0 0x000 ALT0 0x0
 #endif
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index c235a5f..1716d51 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -63,8 +63,8 @@
 
 &qspi {
 	status = "okay";
-	flash@0 {
-		compatible = "n25q512a11";
+	flash0: flash@0 {
+		compatible = "n25q512a11", "spi-flash";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
index 3bd73a0..72184fd 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -22,6 +22,9 @@
 void enable_ocotp_clk(unsigned char enable);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 u32 get_lpuart_clk(void);
+#ifdef CONFIG_SYS_I2C_MXC
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+#endif
 
 #define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
 
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 9fce49d..0c9ed52 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -200,6 +200,7 @@
 #define CCM_REG_CTRL_MASK			0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR0_UART2_CTRL_MASK		(0x3 << 18)
 #define CCM_CCGR0_DSPI0_CTRL_MASK		(0x3 << 24)
 #define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
index c7da2b8..03e3cec 100644
--- a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_ARCH_VF610_DDRMC_H
 #define __ASM_ARCH_VF610_DDRMC_H
 
+#include <asm/arch/iomux-vf610.h>
+
 struct ddr3_jedec_timings {
 	u8 tinit;
 	u32 trst_pwron;
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 5d1f63c..ae0a187 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -289,6 +289,8 @@
 #define SRC_SRSR_WDOG_M4				(0x1 << 4)
 #define SRC_SRSR_WDOG_A5				(0x1 << 3)
 #define SRC_SRSR_POR_RST				(0x1 << 0)
+#define SRC_SBMR1_BOOTCFG1_SDMMC        BIT(6)
+#define SRC_SBMR1_BOOTCFG1_MMC          BIT(4)
 #define SRC_SBMR2_BMOD_MASK             (0x3 << 24)
 #define SRC_SBMR2_BMOD_SHIFT            24
 #define SRC_SBMR2_BMOD_FUSES            0x0
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 01bc299..8ba03e5 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -132,10 +132,14 @@
 	VF610_PAD_PTD24__GPIO_70		= IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD23__NF_IO7			= IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
 	VF610_PAD_PTD0__QSPI0_A_QSCK		= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD0__UART2_TX		= IOMUX_PAD(0x013c, 0x013c, 2, 0x38c, 2, VF610_UART_PAD_CTRL),
 	VF610_PAD_PTD1__QSPI0_A_CS0		= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD1__UART2_RX		= IOMUX_PAD(0x0140, 0x0140, 2, 0x388, 2, VF610_UART_PAD_CTRL),
 	VF610_PAD_PTD2__QSPI0_A_DATA3		= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD2__GPIO_81			= IOMUX_PAD(0x0144, 0x0144, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD3__QSPI0_A_DATA2		= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD4__GPIO_83         = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD3__GPIO_82			= IOMUX_PAD(0x0148, 0x0148, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD4__GPIO_83			= IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
 	VF610_PAD_PTD4__QSPI0_A_DATA1		= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD5__QSPI0_A_DATA0		= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTD7__QSPI0_B_QSCK		= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
diff --git a/arch/arm/include/asm/mach-imx/video.h b/arch/arm/include/asm/mach-imx/video.h
index 812e6f8..d1a14ad 100644
--- a/arch/arm/include/asm/mach-imx/video.h
+++ b/arch/arm/include/asm/mach-imx/video.h
@@ -26,4 +26,5 @@
 #endif
 
 int ipu_set_ldb_clock(int rate);
+int ipu_displays_init(void);
 #endif
diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
index 458319a..0bfdb8d 100644
--- a/arch/arm/lib/interrupts_64.c
+++ b/arch/arm/lib/interrupts_64.c
@@ -25,6 +25,11 @@
 	return 0;
 }
 
+static void show_efi_loaded_images(struct pt_regs *regs)
+{
+	efi_print_image_infos((void *)regs->elr);
+}
+
 void show_regs(struct pt_regs *regs)
 {
 	int i;
@@ -49,6 +54,7 @@
 	efi_restore_gd();
 	printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
+	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
 }
 
@@ -60,6 +66,7 @@
 	efi_restore_gd();
 	printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
+	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
 }
 
@@ -71,6 +78,7 @@
 	efi_restore_gd();
 	printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
+	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
 }
 
@@ -82,6 +90,7 @@
 	efi_restore_gd();
 	printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
+	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
 }
 
@@ -93,6 +102,7 @@
 	efi_restore_gd();
 	printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
+	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
 }
 
@@ -104,6 +114,7 @@
 	efi_restore_gd();
 	printf("\"Irq\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
+	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
 }
 
@@ -115,6 +126,7 @@
 	efi_restore_gd();
 	printf("\"Fiq\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
+	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
 }
 
@@ -129,5 +141,6 @@
 	efi_restore_gd();
 	printf("\"Error\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
+	show_efi_loaded_images(pt_regs);
 	panic("Resetting CPU ...\n");
 }
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8631fbd..ec09ef2 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -23,7 +23,7 @@
 
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6
+	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
 	help
 	  bootaux [addr] to boot auxiliary core.
 
diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c
index 953fe53..22a371a 100644
--- a/arch/arm/mach-imx/video.c
+++ b/arch/arm/mach-imx/video.c
@@ -4,6 +4,17 @@
 #include <linux/errno.h>
 #include <asm/mach-imx/video.h>
 
+#ifdef CONFIG_IMX_HDMI
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/io.h>
+
+int detect_hdmi(struct display_info_t const *dev)
+{
+	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+}
+#endif
+
 int board_video_skip(void)
 {
 	int i;
@@ -42,6 +53,11 @@
 			       displays[i].mode.name,
 			       displays[i].mode.xres,
 			       displays[i].mode.yres);
+
+#ifdef CONFIG_IMX_HDMI
+			if (!strcmp(displays[i].mode.name, "HDMI"))
+				imx_enable_hdmi_phy();
+#endif
 		} else
 			printf("LCD %s cannot be configured: %d\n",
 			       displays[i].mode.name, ret);
@@ -53,12 +69,7 @@
 	return ret;
 }
 
-#ifdef CONFIG_IMX_HDMI
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/io.h>
-int detect_hdmi(struct display_info_t const *dev)
+int ipu_displays_init(void)
 {
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+	return board_video_skip();
 }
-#endif
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index f083a4a..fddbac9 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -9,10 +9,6 @@
 	prompt "OMAP5 board select"
 	optional
 
-config TARGET_CL_SOM_AM57X
-	bool "CompuLab CL-SOM-AM57x"
-	select DRA7XX
-
 config TARGET_CM_T54
 	bool "CompuLab CM-T54"
 
@@ -160,7 +156,6 @@
 endmenu
 endif
 
-source "board/compulab/cl-som-am57x/Kconfig"
 source "board/compulab/cm_t54/Kconfig"
 source "board/ti/omap5_uevm/Kconfig"
 source "board/ti/dra7xx/Kconfig"
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 31b73ed..e186296 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -9,6 +9,7 @@
 
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
+int cpu_has_been_warmreset(void);
 
 void socfpga_bridges_reset(int enable);
 
@@ -47,6 +48,8 @@
 #define RSTMGR_MPUMODRST_CORE0		0
 #define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
 #define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
+/* Watchdogs and MPU warm reset mask */
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK	0x000F0F00
 
 /*
  * Define a reset identifier, from which a permodrst bank ID
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index a238d5d..c412085 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -7,10 +7,6 @@
 
 #ifndef __ASSEMBLY__
 
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
 const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
 
 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
index ca68594..f39206c 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -22,6 +22,7 @@
 #define ECCCTRL1			0x100
 #define ECCCTRL2			0x104
 #define ERRINTEN			0x110
+#define ERRINTENS			0x114
 #define INTMODE				0x11c
 #define INTSTAT				0x120
 #define AUTOWB_CORRADDR			0x138
@@ -52,6 +53,10 @@
 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
 
+#define	DDR_HMC_ERRINTEN_INTMASK				\
+		(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |	\
+		 DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
+
 /* NOC DDR scheduler */
 #define DDR_SCH_ID_COREID		0
 #define DDR_SCH_ID_REVID		0x4
@@ -180,4 +185,8 @@
 #define CALTIMING9_CFG_4_ACT_TO_ACT(x)			\
 	(((x) >> 0) & 0xFF)
 
+/* Firewall DDR scheduler MPFE */
+#define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
+#define FW_HMC_ADAPTOR_MPU_MASK			BIT(0)
+
 #endif /* _SDRAM_S10_H_ */
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 6e11ba6..9865f5b 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -201,16 +201,6 @@
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add(&altera_fpga[0]);
 
-#ifdef CONFIG_DESIGNWARE_SPI
-	/* Get Designware SPI controller out of reset */
-	socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
-	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
-#endif
-
-#ifdef CONFIG_NAND_DENALI
-	socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
-#endif
-
 	return 0;
 }
 
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index f176c38..f8dd787 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -103,3 +103,12 @@
 	writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
 	writel(0, &reset_manager_base->per0modrst);
 }
+
+/*
+ * Return non-zero if the CPU has been warm reset
+ */
+int cpu_has_been_warmreset(void)
+{
+	return readl(&reset_manager_base->status) &
+		RSTMGR_L4WD_MPU_WARMRESET_MASK;
+}
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 142b60f..9dd0afb 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -21,6 +21,7 @@
 #include <debug_uart.h>
 #include <fdtdec.h>
 #include <watchdog.h>
+#include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -38,16 +39,12 @@
 		return BOOT_DEVICE_RAM;
 	case 0x2:	/* NAND Flash (1.8V) */
 	case 0x3:	/* NAND Flash (3.0V) */
-		socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 		return BOOT_DEVICE_NAND;
 	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
 	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
-		socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
-		socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
 		return BOOT_DEVICE_MMC1;
 	case 0x6:	/* QSPI Flash (1.8V) */
 	case 0x7:	/* QSPI Flash (3.0V) */
-		socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
 		return BOOT_DEVICE_SPI;
 	default:
 		printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -123,9 +120,9 @@
 void board_init_f(ulong dummy)
 {
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
-	unsigned long sdram_size;
 	unsigned long reg;
 	int ret;
+	struct udevice *dev;
 
 	/*
 	 * First C code to run. Clear fake OCRAM ECC first as SBE
@@ -156,10 +153,7 @@
 		socfpga_bridges_reset(1);
 	}
 
-	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-
 	timer_init();
 
 	debug("Reconfigure Clock Manager\n");
@@ -181,8 +175,7 @@
 	sysmgr_pinmux_init();
 	sysmgr_config_warmrstcfgio(0);
 
-	/* De-assert reset for peripherals and bridges based on handoff */
-	reset_deassert_peripherals_handoff();
+	/* De-assert reset for bridges based on handoff */
 	socfpga_bridges_reset(0);
 
 	debug("Unfreezing/Thaw all I/O banks\n");
@@ -200,27 +193,16 @@
 		hang();
 	}
 
+	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+	if (ret)
+		debug("Reset init failed: %d\n", ret);
+
 	/* enable console uart printing */
 	preloader_console_init();
 
-	if (sdram_mmr_init_full(0xffffffff) != 0) {
-		puts("SDRAM init failed.\n");
-		hang();
-	}
-
-	debug("SDRAM: Calibrating PHY\n");
-	/* SDRAM calibration */
-	if (sdram_calibration_full() == 0) {
-		puts("SDRAM calibration failed.\n");
-		hang();
-	}
-
-	sdram_size = sdram_calculate_size();
-	debug("SDRAM: %ld MiB\n", sdram_size >> 20);
-
-	/* Sanity check ensure correct SDRAM size specified */
-	if (get_ram_size(0, sdram_size) != sdram_size) {
-		puts("SDRAM size check failed!\n");
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
 		hang();
 	}
 
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a3db20a..a141ffe 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -181,17 +181,6 @@
 		hang();
 	}
 
-	gd->ram_size = sdram_calculate_size();
-	printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
-
-	/* Sanity check ensure correct SDRAM size specified */
-	debug("DDR: Running SDRAM size sanity check\n");
-	if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
-		puts("DDR: SDRAM size check failed!\n");
-		hang();
-	}
-	debug("DDR: SDRAM size check passed!\n");
-
 	mbox_init();
 
 #ifdef CONFIG_CADENCE_QSPI
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 8110f23..1669e62 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -154,8 +154,6 @@
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
-	select DM_MMC if MMC
-	select DM_SCSI if SCSI
 	select PHY_SUN4I_USB
 	select DRAM_SUN4I
 	select SUNXI_GEN_SUN4I
@@ -165,7 +163,6 @@
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
-	select DM_MMC if MMC
 	select DRAM_SUN4I
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
@@ -178,7 +175,6 @@
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
-	select DM_MMC if MMC
 	select DRAM_SUN6I
 	select PHY_SUN4I_USB
 	select SUN6I_P2WI
@@ -205,7 +201,6 @@
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
-	select DM_MMC if MMC
 	select DRAM_SUN8I_A23
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
@@ -219,7 +214,6 @@
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
-	select DM_MMC if MMC
 	select DRAM_SUN8I_A33
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
@@ -230,7 +224,6 @@
 config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
-	select DM_MMC if MMC
 	select DRAM_SUN8I_A83T
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
@@ -246,7 +239,6 @@
 	select ARCH_SUPPORT_PSCI
 	select MACH_SUNXI_H3_H5
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
-	select DM_MMC if MMC
 
 config MACH_SUN8I_R40
 	bool "sun8i (Allwinner R40)"
@@ -265,7 +257,6 @@
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
-	select DM_MMC if MMC
 	select SUNXI_GEN_SUN6I
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_16BIT
@@ -280,13 +271,11 @@
 	select SUNXI_GEN_SUN6I
 	select SUN8I_RSB
 	select SUPPORT_SPL
-	select DM_MMC if MMC
 
 config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
 	select DM_I2C
-	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUN6I_PRCM
 	select SUNXI_DE2
@@ -303,7 +292,6 @@
 	bool "sun50i (Allwinner H5)"
 	select ARM64
 	select MACH_SUNXI_H3_H5
-	select DM_MMC if MMC
 	select FIT
 	select SPL_LOAD_FIT
 
@@ -311,7 +299,6 @@
 	bool "sun50i (Allwinner H6)"
 	select ARM64
 	select SUPPORT_SPL
-	select DM_MMC if MMC
 	select FIT
 	select SPL_LOAD_FIT
 	select DRAM_SUN50I_H6
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index f6f5414..b52ac17 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -27,6 +27,7 @@
 	/* Delay is required for clocks to be propagated */
 	udelay(1000000);
 
+	debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
 	/* Clear the BSS */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -85,7 +86,7 @@
 	case SD_MODE1:
 	case SD1_LSHFT_MODE: /* not working on silicon v1 */
 /* if both controllers enabled, then these two are the second controller */
-#if defined(SPL_ZYNQMP_TWO_SDHCI)
+#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
 		return BOOT_DEVICE_MMC2;
 /* else, fall through, the one SDHCI controller that is enabled is number 1 */
 #endif
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
index b33a75c..63b1057 100644
--- a/board/aristainetos/aristainetos-v2.c
+++ b/board/aristainetos/aristainetos-v2.c
@@ -33,7 +33,7 @@
 #include <micrel.h>
 #include <spi.h>
 #include <video.h>
-#include <../drivers/video/ipu.h>
+#include <../drivers/video/imx/ipu.h>
 #if defined(CONFIG_VIDEO_BMP_LOGO)
 	#include <bmp_logo.h>
 #endif
diff --git a/board/compulab/cl-som-am57x/Kconfig b/board/compulab/cl-som-am57x/Kconfig
deleted file mode 100644
index 85fc9a1..0000000
--- a/board/compulab/cl-som-am57x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CL_SOM_AM57X
-
-config SYS_BOARD
-	default "cl-som-am57x"
-
-config SYS_VENDOR
-	default "compulab"
-
-config SYS_CONFIG_NAME
-	default "cl-som-am57x"
-
-endif
diff --git a/board/compulab/cl-som-am57x/MAINTAINERS b/board/compulab/cl-som-am57x/MAINTAINERS
deleted file mode 100644
index e0195f4..0000000
--- a/board/compulab/cl-som-am57x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CL-SOM-AM57x BOARD
-M:	Uri Mashiach <uri.mashiach@compulab.co.il>
-S:	Maintained
-F:	board/compulab/cl-som-am57x/
-F:	include/configs/cl-som-am57x.h
-F:	configs/cl-som-am57x_defconfig
diff --git a/board/compulab/cl-som-am57x/Makefile b/board/compulab/cl-som-am57x/Makefile
deleted file mode 100644
index 566366b..0000000
--- a/board/compulab/cl-som-am57x/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Makefile
-#
-# (C) Copyright 2016 CompuLab, Ltd. <www.compulab.co.il>
-#
-# Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o mux.o
-else
-obj-y	+= cl-som-am57x.o mux.o
-endif
-
-obj-$(CONFIG_DRIVER_TI_CPSW)	+= eth.o
diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c b/board/compulab/cl-som-am57x/cl-som-am57x.c
deleted file mode 100644
index fcba2a0..0000000
--- a/board/compulab/cl-som-am57x/cl-som-am57x.c
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board functions for CompuLab cl_som_am57x board
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- */
-
-#include <common.h>
-#include <palmas.h>
-#include <usb.h>
-#include <asm/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include "../common/common.h"
-#include "../common/eeprom.h"
-#include <asm/omap_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
-	"Board: CL-SOM-AM57x\n"
-};
-
-int board_init(void)
-{
-	/* Disable PMIC Powerhold feature, DEV_CTRL.DEV_ON = 1 */
-	palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
-
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-#ifdef CONFIG_MMC
-#define SB_SOM_CD_GPIO 187
-#define SB_SOM_WP_GPIO 188
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret0, ret1;
-
-	ret0 = omap_mmc_init(0, 0, 0, SB_SOM_CD_GPIO, SB_SOM_WP_GPIO);
-	if (ret0)
-		printf("cl-som-am57x: failed to initialize mmc0\n");
-
-	ret1 = omap_mmc_init(1, 0, 0, -1, -1);
-	if (ret1)
-		printf("cl-som-am57x: failed to initialize mmc1\n");
-
-	return ret0 && ret1;
-}
-#endif /* CONFIG_MMC */
-
-int misc_init_r(void)
-{
-	cl_print_pcb_info();
-
-	return 0;
-}
-
-u32 get_board_rev(void)
-{
-	return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
-}
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	enable_usb_clocks(index);
-	return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	disable_usb_clocks(index);
-	return 0;
-}
diff --git a/board/compulab/cl-som-am57x/eth.c b/board/compulab/cl-som-am57x/eth.c
deleted file mode 100644
index 3c59457..0000000
--- a/board/compulab/cl-som-am57x/eth.c
+++ /dev/null
@@ -1,198 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Ethernet specific code for CompuLab CL-SOM-AM57x module
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#include <common.h>
-#include <cpsw.h>
-#include <environment.h>
-#include <miiphy.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include "../common/eeprom.h"
-
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-}
-
-static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_addr	= 0,
-		.phy_if         = PHY_INTERFACE_MODE_RMII,
-	},
-	{
-		.slave_reg_ofs	= 0x308,
-		.sliver_reg_ofs	= 0xdc0,
-		.phy_addr	= 1,
-		.phy_if         = PHY_INTERFACE_MODE_RMII,
-
-	},
-};
-
-static struct cpsw_platform_data cl_som_am57_cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 2,
-	.slave_data		= cl_som_am57x_cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-
-/*
- * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address.
- *       The information is retrieved from the SOC's registers.
- * @buff: read buffer.
- * @port_num: port number.
- */
-static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num)
-{
-	uint32_t mac_hi, mac_lo;
-
-	if (port_num) {
-		mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
-		mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
-	} else {
-		mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
-		mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
-	}
-
-	buff[0] = (mac_hi & 0xFF0000) >> 16;
-	buff[1] = (mac_hi & 0xFF00) >> 8;
-	buff[2] = mac_hi & 0xFF;
-	buff[3] = (mac_lo & 0xFF0000) >> 16;
-	buff[4] = (mac_lo & 0xFF00) >> 8;
-	buff[5] = mac_lo & 0xFF;
-}
-
-/*
- * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot
- *	environment.
- *      The address is retrieved retrieved from an EEPROM field or from the
- *	SOC's registers.
- * @env_name: U-Boot environment name.
- * @field_name: EEPROM field name.
- * @port_num: SOC's port number.
- */
-static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num)
-{
-	int ret;
-	uint8_t enetaddr[6];
-
-	ret = eth_env_get_enetaddr(env_name, enetaddr);
-	if (ret)
-		return 0;
-
-	ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
-
-	if (ret || !is_valid_ethaddr(enetaddr))
-		cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num);
-
-	if (!is_valid_ethaddr(enetaddr))
-		return -1;
-
-	ret = eth_env_set_enetaddr(env_name, enetaddr);
-	if (ret)
-		printf("cl-som-am57x: Failed to set Eth port %d MAC address\n",
-		       port_num);
-
-	return ret;
-}
-
-#define CL_SOM_AM57X_PHY_ADDR2			0x01
-#define AR8033_PHY_DEBUG_ADDR_REG		0x1d
-#define AR8033_PHY_DEBUG_DATA_REG		0x1e
-#define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG	0x00
-#define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG	0x05
-#define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK	(1 << 15)
-#define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK	(1 << 8)
-
-/*
- * cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay.
- *	Enable RX delay, disable TX delay.
- */
-static void cl_som_am57x_rgmii_clk_delay(void)
-{
-	uint16_t mii_reg_val;
-	const char *devname;
-
-	devname = miiphy_get_current_dev();
-	/* PHY 2 */
-	miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG,
-		     AR8033_DEBUG_RGMII_RX_CLK_DLY_REG);
-	miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
-		    &mii_reg_val);
-	mii_reg_val |= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK;
-	miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
-		     mii_reg_val);
-
-	miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG,
-		     AR8033_DEBUG_RGMII_TX_CLK_DLY_REG);
-	miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
-		    &mii_reg_val);
-	mii_reg_val &= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK;
-	miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
-		     mii_reg_val);
-}
-
-#define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */
-#define CL_SOM_AM57X_RGMII_PORT1 1
-
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-	uint32_t ctrl_val;
-	char *cpsw_phy_envval;
-	int cpsw_act_phy = 1;
-
-	/* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */
-	ret = cl_som_am57x_handle_mac_address("ethaddr",
-					      CL_SOM_AM57X_RGMII_PORT1);
-
-	if (ret)
-		return -1;
-
-	/* Select RGMII for GMII1_SEL */
-	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
-	ctrl_val |= 0x22;
-	writel(ctrl_val, (*ctrl)->control_core_control_io1);
-	mdelay(10);
-
-	gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST, "phy1_rst");
-	gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST, 0);
-	mdelay(20);
-
-	gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST, 1);
-	mdelay(20);
-
-	cpsw_phy_envval = env_get("cpsw_phy");
-	if (cpsw_phy_envval != NULL)
-		cpsw_act_phy = simple_strtoul(cpsw_phy_envval, NULL, 0);
-
-	cl_som_am57_cpsw_data.active_slave = cpsw_act_phy;
-
-	ret = cpsw_register(&cl_som_am57_cpsw_data);
-	if (ret < 0)
-		printf("Error %d registering CPSW switch\n", ret);
-
-	/* Set RGMII clock delay */
-	cl_som_am57x_rgmii_clk_delay();
-
-	return ret;
-}
diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c
deleted file mode 100644
index 050f2aa..0000000
--- a/board/compulab/cl-som-am57x/mux.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Pinmux configuration for CompuLab CL-SOM-AM57x board
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- */
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux_dra7xx.h>
-
-/* Serial console */
-static const struct pad_conf_entry cl_som_am57x_padconf_console[] = {
-	{UART3_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_RXD */
-	{UART3_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_TXD */
-};
-
-/* PMIC I2C */
-static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = {
-	{MCASP1_ACLKR, (M10 | PIN_INPUT)}, /* MCASP1_ACLKR.I2C4_SDA */
-	{MCASP1_FSR,   (M10 | PIN_INPUT)}, /* MCASP1_FSR.I2C4_SCL */
-};
-
-/* Green GPIO led */
-static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = {
-	{GPMC_A15, (M14 | PIN_OUTPUT_PULLDOWN)}, /* GPMC_A15.GPIO2_5 */
-};
-
-/* MMC/SD Card */
-static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = {
-	{MMC1_CLK,  (M0  | PIN_INPUT_PULLUP)}, /* MMC1_CLK */
-	{MMC1_CMD,  (M0  | PIN_INPUT_PULLUP)}, /* MMC1_CMD */
-	{MMC1_DAT0, (M0  | PIN_INPUT_PULLUP)}, /* MMC1_DAT0 */
-	{MMC1_DAT1, (M0  | PIN_INPUT_PULLUP)}, /* MMC1_DAT1 */
-	{MMC1_DAT2, (M0  | PIN_INPUT_PULLUP)}, /* MMC1_DAT2 */
-	{MMC1_DAT3, (M0  | PIN_INPUT_PULLUP)}, /* MMC1_DAT3 */
-	{MMC1_SDCD, (M14 | PIN_INPUT)       }, /* MMC1_SDCD */
-	{MMC1_SDWP, (M14 | PIN_INPUT)       }, /* MMC1_SDWP */
-};
-
-/* WiFi - must be in the safe mode on boot */
-static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = {
-	{UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_CTSN */
-	{UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_RTSN */
-	{UART2_RXD,  (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RXD */
-	{UART2_TXD,  (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_TXD */
-	{UART2_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_CTSN */
-	{UART2_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RTSN */
-};
-
-/* QSPI */
-static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = {
-	{GPMC_A13, (M1 | PIN_INPUT)       }, /* GPMC_A13.QSPI1_RTCLK */
-	{GPMC_A18, (M1 | PIN_INPUT)       }, /* GPMC_A18.QSPI1_SCLK */
-	{GPMC_A16, (M1 | PIN_INPUT)       }, /* GPMC_A16.QSPI1_D0 */
-	{GPMC_A17, (M1 | PIN_INPUT)       }, /* GPMC_A17.QSPI1_D1 */
-	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */
-};
-
-/* GPIO Expander I2C */
-static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = {
-	{MCASP1_AXR0, (M10 | PIN_INPUT)}, /* MCASP1_AXR0.I2C5_SDA */
-	{MCASP1_AXR1, (M10 | PIN_INPUT)}, /* MCASP1_AXR1.I2C5_SCL */
-};
-
-/* eMMC internal storage */
-static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = {
-	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */
-	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */
-	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */
-	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */
-	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */
-	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A24.MMC2_DAT0 */
-	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A25.MMC2_DAT1 */
-	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A26.MMC2_DAT2 */
-	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A27.MMC2_DAT3 */
-	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS1.MMC2_CMD */
-};
-
-/* usb1_drvvbus */
-static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = {
-	/* USB1_DRVVBUS.USB1_DRVVBUS */
-	{USB1_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL) },
-};
-
-/* Ethernet */
-static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = {
-	/* MDIO bus */
-	{VIN2A_D10,  (M3  | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK  */
-	{VIN2A_D11,  (M3  | PIN_INPUT_PULLUP)  }, /* VIN2A_D11.MDIO_D  */
-	/* EMAC Slave 1 at addr 0x1 - Default interface */
-	{VIN2A_D12,  (M3  | PIN_OUTPUT)         }, /* VIN2A_D12.RGMII1_TXC */
-	{VIN2A_D13,  (M3  | PIN_OUTPUT)         }, /* VIN2A_D13.RGMII1_TXCTL */
-	{VIN2A_D14,  (M3  | PIN_OUTPUT)         }, /* VIN2A_D14.RGMII1_TXD3 */
-	{VIN2A_D15,  (M3  | PIN_OUTPUT)         }, /* VIN2A_D15.RGMII1_TXD2 */
-	{VIN2A_D16,  (M3  | PIN_OUTPUT)         }, /* VIN2A_D16.RGMII1_TXD1 */
-	{VIN2A_D17,  (M3  | PIN_OUTPUT)         }, /* VIN2A_D17.RGMII1_TXD0 */
-	{VIN2A_D18,  (M3  | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */
-	{VIN2A_D19,  (M3  | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */
-	{VIN2A_D20,  (M3  | PIN_INPUT_PULLDOWN) }, /* VIN2A_D20.RGMII1_RXD3 */
-	{VIN2A_D21,  (M3  | PIN_INPUT_PULLDOWN) }, /* VIN2A_D21.RGMII1_RXD2 */
-	{VIN2A_D22,  (M3  | PIN_INPUT_PULLDOWN) }, /* VIN2A_D22.RGMII1_RXD1 */
-	{VIN2A_D23,  (M3  | PIN_INPUT_PULLDOWN) }, /* VIN2A_D23.RGMII1_RXD0 */
-	/* Eth PHY1 reset GPIOs*/
-	{VIN2A_CLK0, (M14 | PIN_OUTPUT_PULLDOWN)}, /* VIN2A_CLK0.GPIO3_28 */
-};
-
-#define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \
-					mux_array, ARRAY_SIZE(mux_array))
-
-void set_muxconf_regs(void)
-{
-	SET_MUX(cl_som_am57x_padconf_console);
-	SET_MUX(cl_som_am57x_padconf_pmic);
-	SET_MUX(cl_som_am57x_padconf_green_led);
-	SET_MUX(cl_som_am57x_padconf_sd_card);
-	SET_MUX(cl_som_am57x_padconf_wifi);
-	SET_MUX(cl_som_am57x_padconf_qspi);
-	SET_MUX(cl_som_am57x_padconf_i2c_gpio);
-	SET_MUX(cl_som_am57x_padconf_emmc);
-	SET_MUX(cl_som_am57x_padconf_usb);
-	SET_MUX(cl_som_am57x_padconf_ethernet);
-}
diff --git a/board/compulab/cl-som-am57x/spl.c b/board/compulab/cl-som-am57x/spl.c
deleted file mode 100644
index 0fb3d84..0000000
--- a/board/compulab/cl-som-am57x/spl.c
+++ /dev/null
@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPL data and initialization for CompuLab CL-SOM-AM57x board
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#include <asm/emif.h>
-#include <asm/omap_common.h>
-#include <asm/arch/sys_proto.h>
-
-static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
-	.dmm_lisa_map_3 = 0x80740300,
-	.is_ma_present  = 0x1
-};
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
-{
-	/* Disable SDRAM controller EMIF2 for single core SOC */
-	*dmm_lisa_regs = &cl_som_am57x_lisa_regs;
-	if (omap_revision() == DRA722_ES1_0) {
-		((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 =
-		  0x80640100;
-	}
-}
-
-static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
-	.sdram_config_init	= 0x61852332,
-	.sdram_config		= 0x61852332,
-	.sdram_config2		= 0x00000000,
-	.ref_ctrl		= 0x000040f1,
-	.ref_ctrl_final		= 0x00001040,
-	.sdram_tim1		= 0xeeef36f3,
-	.sdram_tim2		= 0x348f7fda,
-	.sdram_tim3		= 0x027f88a8,
-	.read_idle_ctrl		= 0x00050000,
-	.zq_config		= 0x1007190b,
-	.temp_alert_config	= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init = 0x0034400b,
-	.emif_ddr_phy_ctlr_1	= 0x0e34400b,
-	.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
-	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
-	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
-	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
-	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
-	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
-	.emif_rd_wr_lvl_ctl	= 0x00000000,
-	.emif_rd_wr_exec_thresh	= 0x00000305
-};
-
-/* Ext phy ctrl regs 1-35 */
-static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
-	0x10040100,
-	0x00740074,
-	0x00780078,
-	0x007c007c,
-	0x007b007b,
-	0x00800080,
-	0x00360036,
-	0x00340034,
-	0x00360036,
-	0x00350035,
-	0x00350035,
-
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-
-	0x00430043,
-	0x003e003e,
-	0x004a004a,
-	0x00470047,
-	0x00400040,
-
-	0x00000000,
-	0x00600020,
-	0x40011080,
-	0x08102040,
-
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0
-};
-
-static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
-	.sdram_config_init	= 0x61852332,
-	.sdram_config		= 0x61852332,
-	.sdram_config2		= 0x00000000,
-	.ref_ctrl		= 0x000040f1,
-	.ref_ctrl_final		= 0x00001040,
-	.sdram_tim1		= 0xeeef36f3,
-	.sdram_tim2		= 0x348f7fda,
-	.sdram_tim3		= 0x027f88a8,
-	.read_idle_ctrl		= 0x00050000,
-	.zq_config		= 0x1007190b,
-	.temp_alert_config	= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init = 0x0034400b,
-	.emif_ddr_phy_ctlr_1	= 0x0e34400b,
-	.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
-	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
-	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
-	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
-	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
-	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
-	.emif_rd_wr_lvl_ctl	= 0x00000000,
-	.emif_rd_wr_exec_thresh	= 0x00000305
-};
-
-static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
-	0x10040100,
-	0x00820082,
-	0x008b008b,
-	0x00800080,
-	0x007e007e,
-	0x00800080,
-	0x00370037,
-	0x00390039,
-	0x00360036,
-	0x00370037,
-	0x00350035,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x00540054,
-	0x00540054,
-	0x004e004e,
-	0x004c004c,
-	0x00400040,
-
-	0x00000000,
-	0x00600020,
-	0x40011080,
-	0x08102040,
-
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0
-};
-
-static struct vcores_data cl_som_am57x_volts = {
-	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
-	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
-	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
-	.mpu.pmic		= &tps659038,
-
-	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
-	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
-	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
-	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
-	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
-	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
-	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
-	.eve.pmic		= &tps659038,
-
-	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
-	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
-	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
-	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
-	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
-	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
-	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.gpu.addr		= TPS659038_REG_ADDR_SMPS6,
-	.gpu.pmic		= &tps659038,
-
-	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
-	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
-	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.core.addr		= TPS659038_REG_ADDR_SMPS7,
-	.core.pmic		= &tps659038,
-
-	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
-	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
-	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
-	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
-	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
-	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
-	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.iva.addr		= TPS659038_REG_ADDR_SMPS8,
-	.iva.pmic		= &tps659038,
-};
-
-void hw_data_init(void)
-{
-	*prcm = &dra7xx_prcm;
-	*dplls_data = &dra7xx_dplls;
-	*omap_vcores = &cl_som_am57x_volts;
-	*ctrl = &dra7xx_ctrl;
-}
-
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
-{
-	switch (emif_nr) {
-	case 1:
-		*regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
-		break;
-	case 2:
-		*regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
-		break;
-	}
-}
-
-void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
-{
-	switch (emif_nr) {
-	case 1:
-		*regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
-		*size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
-		break;
-	case 2:
-		*regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
-		*size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);
-		break;
-	}
-}
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index a4c587a..63cd605 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -112,7 +112,7 @@
 	sc_misc_build_info(-1, &sc_build, &sc_commit);
 	if (!sc_build) {
 		printf("SCFW does not support build info\n");
-		sc_commit = 0; /* Display 0 when the build info is not supported*/
+		sc_commit = 0; /* Display 0 when the build info is not supported */
 	}
 	printf("Build: SCFW %x\n", sc_commit);
 }
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 079d302..f42d2ce 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -10,6 +10,7 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <linux/errno.h>
+#include <linux/libfdt.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/iomux-v3.h>
@@ -27,6 +28,7 @@
 #include <i2c.h>
 #include <input.h>
 #include <pwm.h>
+#include <version.h>
 #include <stdlib.h>
 #include "../common/ge_common.h"
 #include "../common/vpd_reader.h"
@@ -44,10 +46,6 @@
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
 	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
 
@@ -57,9 +55,6 @@
 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
 	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
@@ -110,58 +105,13 @@
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 
 	/* Reset AR8033 PHY */
+	gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
 	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 	mdelay(1);
 }
 
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
@@ -201,18 +151,6 @@
 	}
 };
 
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
-}
-
-static void setup_spi(void)
-{
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-#endif
-
 static iomux_v3_cfg_t const pcie_pads[] = {
 	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -229,76 +167,6 @@
 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC2_BASE_ADDR},
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
-#define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 11)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = 1; /* eMMC is always present */
-		break;
-	case USDHC4_BASE_ADDR:
-		ret = !gpio_get_value(USDHC4_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-	int i;
-
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			gpio_direction_input(USDHC2_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			gpio_direction_input(USDHC4_CD_GPIO);
-			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers\n"
-			       "(%d) then supported by the board (%d)\n",
-			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-#endif
-
 static int mx6_rgmii_rework(struct phy_device *phydev)
 {
 	/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
@@ -533,8 +401,8 @@
 	/* backlights off until needed */
 	imx_iomux_v3_setup_multiple_pads(backlight_pads,
 					 ARRAY_SIZE(backlight_pads));
+	gpio_request(LVDS_POWER_GP, "lvds_power");
 	gpio_direction_input(LVDS_POWER_GP);
-	gpio_direction_input(LVDS_BACKLIGHT_GP);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
@@ -687,20 +555,25 @@
 		set_confidx(&vpd);
 	}
 
+	gpio_request(SUS_S3_OUT, "sus_s3_out");
 	gpio_direction_output(SUS_S3_OUT, 1);
+
+	gpio_request(WIFI_EN, "wifi_en");
 	gpio_direction_output(WIFI_EN, 1);
+
 #if defined(CONFIG_VIDEO_IPUV3)
 	if (is_b850v3())
 		setup_display_b850v3();
 	else
 		setup_display_bx50v3();
+
+	gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
+	gpio_direction_input(LVDS_BACKLIGHT_GP);
 #endif
+
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_MXC_SPI
-	setup_spi();
-#endif
 	return 0;
 }
 
@@ -818,6 +691,15 @@
 	return 0;
 }
 
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	fdt_setprop(blob, 0, "ge,boot-ver", version_string,
+	                                    strlen(version_string) + 1);
+	return 0;
+}
+#endif
+
 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 #ifdef CONFIG_VIDEO_IPUV3
diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c
index 23bfe55..5411e42 100644
--- a/board/ge/mx53ppd/mx53ppd.c
+++ b/board/ge/mx53ppd/mx53ppd.c
@@ -17,6 +17,7 @@
 #include <asm/arch/iomux-mx53.h>
 #include <asm/arch/clock.h>
 #include <linux/errno.h>
+#include <linux/libfdt.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/mx5_video.h>
 #include <environment.h>
@@ -30,6 +31,7 @@
 #include <fsl_pmic.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
+#include <version.h>
 #include <watchdog.h>
 #include "ppd_gpio.h"
 #include <stdlib.h>
@@ -122,79 +124,6 @@
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
-	{MMC_SDHC3_BASE_ADDR},
-	{MMC_SDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	return 1;
-}
-
-#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
-				 PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
-				 PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(bd_t *bis)
-{
-	static const iomux_v3_cfg_t sd1_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-			     SD_CMD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
-		MX53_PAD_EIM_DA11__GPIO3_11,
-	};
-
-	static const iomux_v3_cfg_t sd2_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
-		MX53_PAD_EIM_DA13__GPIO3_13,
-	};
-
-	u32 index;
-	int ret;
-
-	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(sd1_pads,
-							 ARRAY_SIZE(sd1_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(sd2_pads,
-							 ARRAY_SIZE(sd2_pads));
-			break;
-		default:
-			printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n",
-			       CONFIG_SYS_FSL_ESDHC_NUM);
-			return -EINVAL;
-		}
-		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-#endif
-
 #define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 
@@ -380,3 +309,12 @@
 
 	return 0;
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	fdt_setprop(blob, 0, "ge,boot-ver", version_string,
+	                                    strlen(version_string) + 1);
+	return 0;
+}
+#endif
diff --git a/board/ge/mx53ppd/ppd_gpio.h b/board/ge/mx53ppd/ppd_gpio.h
index e3b84c7..ba2d1ba 100644
--- a/board/ge/mx53ppd/ppd_gpio.h
+++ b/board/ge/mx53ppd/ppd_gpio.h
@@ -36,6 +36,8 @@
 	MX53_PAD_KEY_COL2__GPIO4_10,
 	MX53_PAD_KEY_ROW2__GPIO4_11,
 	MX53_PAD_KEY_COL3__GPIO4_12,
+
+	MX53_PAD_PATA_DATA7__GPIO2_7,    /* BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */
 };
 
 struct gpio_cfg {
@@ -61,6 +63,7 @@
 #define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
 #define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
 #define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
+#define BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N IMX_GPIO_NR(2, 7)
 
 static const struct gpio_cfg ppd_gpios[] = {
 	/* FEC */
@@ -90,6 +93,7 @@
 	{ ECSPI1_CS1, 1 },
 	{ ECSPI1_CS2, 1 },
 	{ ECSPI1_CS3, 1 },
+	{ BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N, 1 },
 };
 
 #endif /* __PPD_GPIO_H_ */
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index f988af2..c30df5d 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -1,5 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * (C) Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+ *
  * Copyright 2013 Freescale Semiconductor, Inc.
  */
 
@@ -10,79 +13,12 @@
 #include <asm/arch/ddrmc-vf610.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <led.h>
+#include <environment.h>
 #include <miiphy.h>
-#include <netdev.h>
-#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h
- * do not match our settings. Let us (re)define our own settings here.
- */
-
-#define PCM052_VF610_DDR_PAD_CTRL	PAD_CTL_DSE_20ohm
-#define PCM052_VF610_DDR_PAD_CTRL_1	(PAD_CTL_DSE_20ohm | \
-					PAD_CTL_INPUT_DIFFERENTIAL)
-#define PCM052_VF610_DDR_RESET_PAD_CTL	(PAD_CTL_DSE_150ohm | \
-					PAD_CTL_PUS_100K_UP | \
-					PAD_CTL_INPUT_DIFFERENTIAL)
-
-enum {
-	PCM052_VF610_PAD_DDR_RESETB			= IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL),
-	PCM052_VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A13__DDR_A_13		= IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A12__DDR_A_12		= IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A11__DDR_A_11		= IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A10__DDR_A_10		= IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A9__DDR_A_9		= IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A8__DDR_A_8		= IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A7__DDR_A_7		= IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A6__DDR_A_6		= IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A5__DDR_A_5		= IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A4__DDR_A_4		= IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A3__DDR_A_3		= IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A2__DDR_A_2		= IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A1__DDR_A_1		= IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_A0__DDR_A_0		= IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_BA2__DDR_BA_2		= IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_BA1__DDR_BA_1		= IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_BA0__DDR_BA_0		= IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B		= IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0		= IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0		= IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
-	PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0		= IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D15__DDR_D_15		= IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D14__DDR_D_14		= IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D13__DDR_D_13		= IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D12__DDR_D_12		= IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D11__DDR_D_11		= IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D10__DDR_D_10		= IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D9__DDR_D_9		= IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D8__DDR_D_8		= IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D7__DDR_D_7		= IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D6__DDR_D_6		= IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D5__DDR_D_5		= IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D4__DDR_D_4		= IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D3__DDR_D_3		= IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D2__DDR_D_2		= IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D1__DDR_D_1		= IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_D0__DDR_D_0		= IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1		= IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0		= IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1		= IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
-	PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0		= IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
-	PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B		= IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	= IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-	PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0	= IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
-};
-
 static struct ddrmc_cr_setting pcm052_cr_settings[] = {
 	/* not in the datasheets, but in the original code */
 	{ 0x00002000, 105 },
@@ -151,59 +87,6 @@
 
 int dram_init(void)
 {
-	static const iomux_v3_cfg_t pcm052_pads[] = {
-		PCM052_VF610_PAD_DDR_A15__DDR_A_15,
-		PCM052_VF610_PAD_DDR_A14__DDR_A_14,
-		PCM052_VF610_PAD_DDR_A13__DDR_A_13,
-		PCM052_VF610_PAD_DDR_A12__DDR_A_12,
-		PCM052_VF610_PAD_DDR_A11__DDR_A_11,
-		PCM052_VF610_PAD_DDR_A10__DDR_A_10,
-		PCM052_VF610_PAD_DDR_A9__DDR_A_9,
-		PCM052_VF610_PAD_DDR_A8__DDR_A_8,
-		PCM052_VF610_PAD_DDR_A7__DDR_A_7,
-		PCM052_VF610_PAD_DDR_A6__DDR_A_6,
-		PCM052_VF610_PAD_DDR_A5__DDR_A_5,
-		PCM052_VF610_PAD_DDR_A4__DDR_A_4,
-		PCM052_VF610_PAD_DDR_A3__DDR_A_3,
-		PCM052_VF610_PAD_DDR_A2__DDR_A_2,
-		PCM052_VF610_PAD_DDR_A1__DDR_A_1,
-		PCM052_VF610_PAD_DDR_A0__DDR_A_0,
-		PCM052_VF610_PAD_DDR_BA2__DDR_BA_2,
-		PCM052_VF610_PAD_DDR_BA1__DDR_BA_1,
-		PCM052_VF610_PAD_DDR_BA0__DDR_BA_0,
-		PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B,
-		PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0,
-		PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0,
-		PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0,
-		PCM052_VF610_PAD_DDR_D15__DDR_D_15,
-		PCM052_VF610_PAD_DDR_D14__DDR_D_14,
-		PCM052_VF610_PAD_DDR_D13__DDR_D_13,
-		PCM052_VF610_PAD_DDR_D12__DDR_D_12,
-		PCM052_VF610_PAD_DDR_D11__DDR_D_11,
-		PCM052_VF610_PAD_DDR_D10__DDR_D_10,
-		PCM052_VF610_PAD_DDR_D9__DDR_D_9,
-		PCM052_VF610_PAD_DDR_D8__DDR_D_8,
-		PCM052_VF610_PAD_DDR_D7__DDR_D_7,
-		PCM052_VF610_PAD_DDR_D6__DDR_D_6,
-		PCM052_VF610_PAD_DDR_D5__DDR_D_5,
-		PCM052_VF610_PAD_DDR_D4__DDR_D_4,
-		PCM052_VF610_PAD_DDR_D3__DDR_D_3,
-		PCM052_VF610_PAD_DDR_D2__DDR_D_2,
-		PCM052_VF610_PAD_DDR_D1__DDR_D_1,
-		PCM052_VF610_PAD_DDR_D0__DDR_D_0,
-		PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1,
-		PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0,
-		PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1,
-		PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0,
-		PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B,
-		PCM052_VF610_PAD_DDR_WE__DDR_WE_B,
-		PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0,
-		PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1,
-		PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
-		PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0,
-		PCM052_VF610_PAD_DDR_RESETB,
-	};
-
 #if defined(CONFIG_TARGET_PCM052)
 
 	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
@@ -320,8 +203,6 @@
 
 #endif
 
-	imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
-
 	ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
 			     pcm052_phy_settings, 1, row_diff);
 
@@ -330,135 +211,6 @@
 	return 0;
 }
 
-static void setup_iomux_uart(void)
-{
-	static const iomux_v3_cfg_t uart1_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
-			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-static void setup_iomux_enet(void)
-{
-	static const iomux_v3_cfg_t enet0_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
-}
-
-/*
- * I2C2 is the only I2C used, on pads PTA22/PTA23.
- */
-
-static void setup_iomux_i2c(void)
-{
-	static const iomux_v3_cfg_t i2c_pads[] = {
-		VF610_PAD_PTA22__I2C2_SCL,
-		VF610_PAD_PTA23__I2C2_SDA,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
-#ifdef CONFIG_NAND_VF610_NFC
-static void setup_iomux_nfc(void)
-{
-	static const iomux_v3_cfg_t nfc_pads[] = {
-		VF610_PAD_PTD31__NF_IO15,
-		VF610_PAD_PTD30__NF_IO14,
-		VF610_PAD_PTD29__NF_IO13,
-		VF610_PAD_PTD28__NF_IO12,
-		VF610_PAD_PTD27__NF_IO11,
-		VF610_PAD_PTD26__NF_IO10,
-		VF610_PAD_PTD25__NF_IO9,
-		VF610_PAD_PTD24__NF_IO8,
-		VF610_PAD_PTD23__NF_IO7,
-		VF610_PAD_PTD22__NF_IO6,
-		VF610_PAD_PTD21__NF_IO5,
-		VF610_PAD_PTD20__NF_IO4,
-		VF610_PAD_PTD19__NF_IO3,
-		VF610_PAD_PTD18__NF_IO2,
-		VF610_PAD_PTD17__NF_IO1,
-		VF610_PAD_PTD16__NF_IO0,
-		VF610_PAD_PTB24__NF_WE_B,
-		VF610_PAD_PTB25__NF_CE0_B,
-		VF610_PAD_PTB27__NF_RE_B,
-		VF610_PAD_PTC26__NF_RB_B,
-		VF610_PAD_PTC27__NF_ALE,
-		VF610_PAD_PTC28__NF_CLE
-	};
-
-	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
-}
-#endif
-
-static void setup_iomux_qspi(void)
-{
-	static const iomux_v3_cfg_t qspi0_pads[] = {
-		VF610_PAD_PTD0__QSPI0_A_QSCK,
-		VF610_PAD_PTD1__QSPI0_A_CS0,
-		VF610_PAD_PTD2__QSPI0_A_DATA3,
-		VF610_PAD_PTD3__QSPI0_A_DATA2,
-		VF610_PAD_PTD4__QSPI0_A_DATA1,
-		VF610_PAD_PTD5__QSPI0_A_DATA0,
-		VF610_PAD_PTD7__QSPI0_B_QSCK,
-		VF610_PAD_PTD8__QSPI0_B_CS0,
-		VF610_PAD_PTD9__QSPI0_B_DATA3,
-		VF610_PAD_PTD10__QSPI0_B_DATA2,
-		VF610_PAD_PTD11__QSPI0_B_DATA1,
-		VF610_PAD_PTD12__QSPI0_B_DATA0,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
-}
-
-#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
-			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
-	{ESDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	/* eSDHC1 is always present */
-	return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	static const iomux_v3_cfg_t esdhc1_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
-	};
-
-	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	imx_iomux_v3_setup_multiple_pads(
-		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
-
-	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-
 static void clock_init(void)
 {
 	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
@@ -485,7 +237,7 @@
 	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 			CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
-			CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK);
+			CCM_CCGR10_NFC_CTRL_MASK);
 
 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 			ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
@@ -531,23 +283,10 @@
 		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 }
 
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 int board_early_init_f(void)
 {
 	clock_init();
 	mscm_init();
-	setup_iomux_uart();
-	setup_iomux_enet();
-	setup_iomux_i2c();
-	setup_iomux_qspi();
-	setup_iomux_nfc();
 
 	return 0;
 }
@@ -571,47 +310,102 @@
 	return 0;
 }
 
-int checkboard(void)
+#ifdef CONFIG_TARGET_BK4R1
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
-	puts("Board: PCM-052\n");
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+		(struct fuse_bank4_regs *)bank->fuse_regs;
+	u32 value;
+
+	/*
+	 * BK4 has different layout of stored MAC address
+	 * than one used in imx_get_mac_from_fuse() @ generic.c
+	 */
+
+	switch (dev_id) {
+	case 0:
+		value = readl(&fuse->mac_addr1);
+
+		mac[0] = value >> 8;
+		mac[1] = value;
+
+		value = readl(&fuse->mac_addr0);
+		mac[2] = value >> 24;
+		mac[3] = value >> 16;
+		mac[4] = value >> 8;
+		mac[5] = value;
+		break;
+	case 1:
+		value = readl(&fuse->mac_addr2);
+
+		mac[0] = value >> 24;
+		mac[1] = value >> 16;
+		mac[2] = value >> 8;
+		mac[3] = value;
+
+		value = readl(&fuse->mac_addr1);
+		mac[4] = value >> 24;
+		mac[5] = value >> 16;
+		break;
+	}
+}
+
+int board_late_init(void)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	u32 reg;
+
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	/*
+	 * BK4r1 handle emergency/service SD card boot
+	 * Checking the SBMR1 register BOOTCFG1 byte:
+	 * NAND:
+	 *      bit [2] - NAND data width - 16
+	 *	bit [5] - NAND fast boot
+	 *	bit [7] = 1 - NAND as a source of booting
+	 * SD card (0x64):
+	 *      bit [4] = 0 - SD card source
+	 *	bit [6] = 1 - SD/MMC source
+	 */
+
+	reg = readl(&psrc->sbmr1);
+	if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
+	    !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
+		printf("------ SD card boot -------\n");
+		set_default_env("!LVFBootloader", 0);
+		env_set("bootcmd",
+			"run prepare_install_bk4r1_envs; run install_bk4r1rs");
+	}
 
 	return 0;
 }
 
-static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[])
+/**
+ * KSZ8081
+ */
+#define MII_KSZ8081_REFERENCE_CLOCK_SELECT	0x1f
+#define RMII_50MHz_CLOCK	0x8180
+
+int board_phy_config(struct phy_device *phydev)
 {
-	ulong addr;
+	/* Set 50 MHz reference clock */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
+		  RMII_50MHz_CLOCK);
 
-	/* Consume 'm4go' */
-	argc--; argv++;
-
-	/*
-	 * Parse provided address - default to load_addr in case not provided.
-	 */
-
-	if (argc)
-		addr = simple_strtoul(argv[0], NULL, 16);
-	else
-		addr = load_addr;
-
-	/*
-	 * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0]
-	 */
-	writel(addr + 0x401, 0x4006E028);
-
-	/*
-	 * Start secondary processor by enabling its clock
-	 */
-	writel(0x15a5a, 0x4006B08C);
-
-	return 1;
+	return genphy_config(phydev);
 }
+#endif /* CONFIG_TARGET_BK4R1 */
 
-U_BOOT_CMD(
-	m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go,
-	"start the secondary Cortex-M4 from scatter file image",
-	"[<addr>]\n"
-	"    - start secondary Cortex-M4 core using a scatter file image\n"
-	"The argument needs to be a scatter file\n"
-);
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_BK4R1
+	puts("Board: BK4r1 (L333)\n");
+#else
+	puts("Board: PCM-052\n");
+#endif
+	return 0;
+}
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 24d299a..76917b0 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -7,7 +7,9 @@
 #include <config.h>
 #include <clk.h>
 #include <dm.h>
+#include <g_dnl.h>
 #include <generic-phy.h>
+#include <i2c.h>
 #include <led.h>
 #include <misc.h>
 #include <phy.h>
@@ -58,11 +60,6 @@
  */
 DECLARE_GLOBAL_DATA_PTR;
 
-#define STM32MP_GUSBCFG 0x40002407
-
-#define STM32MP_GGPIO 0x38
-#define STM32MP_GGPIO_VBUS_SENSING BIT(21)
-
 #define USB_WARNING_LOW_THRESHOLD_UV	660000
 #define USB_START_LOW_THRESHOLD_UV	1230000
 #define USB_START_HIGH_THRESHOLD_UV	2100000
@@ -155,150 +152,76 @@
 #endif
 }
 
-static struct dwc2_plat_otg_data stm32mp_otg_data = {
-	.usb_gusbcfg = STM32MP_GUSBCFG,
-};
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
 
-static struct reset_ctl usbotg_reset;
+/* STMicroelectronics STUSB1600 Type-C controller */
+#define STUSB1600_CC_CONNECTION_STATUS		0x0E
 
-int board_usb_init(int index, enum usb_init_type init)
+/* STUSB1600_CC_CONNECTION_STATUS bitfields */
+#define STUSB1600_CC_ATTACH			BIT(0)
+
+static int stusb1600_init(struct udevice **dev_stusb1600)
 {
-	struct fdtdec_phandle_args args;
-	struct udevice *dev;
-	const void *blob = gd->fdt_blob;
-	struct clk clk;
-	struct phy phy;
-	int node;
-	int phy_provider;
+	ofnode node;
+	struct udevice *dev, *bus;
 	int ret;
+	u32 chip_addr;
 
-	/* find the usb otg node */
-	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
-	if (node < 0) {
-		debug("Not found usb_otg device\n");
+	*dev_stusb1600 = NULL;
+
+	/* if node stusb1600 is present, means DK1 or DK2 board */
+	node = ofnode_by_compatible(ofnode_null(), "st,stusb1600");
+	if (!ofnode_valid(node))
 		return -ENODEV;
-	}
 
-	if (!fdtdec_get_is_enabled(blob, node)) {
-		debug("stm32 usbotg is disabled in the device tree\n");
-		return -ENODEV;
-	}
-
-	/* Enable clock */
-	ret = fdtdec_parse_phandle_with_args(blob, node, "clocks",
-					     "#clock-cells", 0, 0, &args);
-	if (ret) {
-		debug("usbotg has no clocks defined in the device tree\n");
-		return ret;
-	}
-
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev);
+	ret = ofnode_read_u32(node, "reg", &chip_addr);
 	if (ret)
-		return ret;
+		return -EINVAL;
 
-	if (args.args_count != 1) {
-		debug("Can't find clock ID in the device tree\n");
-		return -ENODATA;
-	}
-
-	clk.dev = dev;
-	clk.id = args.args[0];
-
-	ret = clk_enable(&clk);
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C, ofnode_get_parent(node),
+					  &bus);
 	if (ret) {
-		debug("Failed to enable usbotg clock\n");
-		return ret;
+		printf("bus for stusb1600 not found\n");
+		return -ENODEV;
 	}
 
-	/* Reset */
-	ret = fdtdec_parse_phandle_with_args(blob, node, "resets",
-					     "#reset-cells", 0, 0, &args);
-	if (ret) {
-		debug("usbotg has no resets defined in the device tree\n");
-		goto clk_err;
-	}
-
-	ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev);
-	if (ret || args.args_count != 1)
-		goto clk_err;
-
-	usbotg_reset.dev = dev;
-	usbotg_reset.id = args.args[0];
-
-	reset_assert(&usbotg_reset);
-	udelay(2);
-	reset_deassert(&usbotg_reset);
-
-	/* Get USB PHY */
-	ret = fdtdec_parse_phandle_with_args(blob, node, "phys",
-					     "#phy-cells", 0, 0, &args);
-	if (!ret) {
-		phy_provider = fdt_parent_offset(blob, args.node);
-		ret = uclass_get_device_by_of_offset(UCLASS_PHY,
-						     phy_provider, &dev);
-		if (ret)
-			goto clk_err;
-
-		phy.dev = dev;
-		phy.id = fdtdec_get_uint(blob, args.node, "reg", -1);
-
-		ret = generic_phy_power_on(&phy);
-		if (ret) {
-			debug("unable to power on the phy\n");
-			goto clk_err;
-		}
-
-		ret = generic_phy_init(&phy);
-		if (ret) {
-			debug("failed to init usb phy\n");
-			goto phy_power_err;
-		}
-	}
-
-	/* Parse and store data needed for gadget */
-	stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-	if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) {
-		debug("usbotg: can't get base address\n");
-		ret = -ENODATA;
-		goto phy_init_err;
-	}
-
-	stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node,
-						     "g-rx-fifo-size", 0);
-	stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node,
-							"g-np-tx-fifo-size", 0);
-	stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node,
-						     "g-tx-fifo-size", 0);
-	/* Enable voltage level detector */
-	if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply",
-					     NULL, 0, 0, &args))) {
-		if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR,
-						    args.node, &dev)) {
-			ret = regulator_set_enable(dev, true);
-			if (ret) {
-				debug("Failed to enable usb33d\n");
-				goto phy_init_err;
-			}
-		}
-	}
-		/* Enable vbus sensing */
-	setbits_le32(stm32mp_otg_data.regs_otg + STM32MP_GGPIO,
-		     STM32MP_GGPIO_VBUS_SENSING);
-
-	return dwc2_udc_probe(&stm32mp_otg_data);
-
-phy_init_err:
-	generic_phy_exit(&phy);
-
-phy_power_err:
-	generic_phy_power_off(&phy);
-
-clk_err:
-	clk_disable(&clk);
+	ret = dm_i2c_probe(bus, chip_addr, 0, &dev);
+	if (!ret)
+		*dev_stusb1600 = dev;
 
 	return ret;
 }
 
+static int stusb1600_cable_connected(struct udevice *dev)
+{
+	u8 status;
+
+	if (dm_i2c_read(dev, STUSB1600_CC_CONNECTION_STATUS, &status, 1))
+		return 0;
+
+	return status & STUSB1600_CC_ATTACH;
+}
+
+#include <usb/dwc2_udc.h>
+int g_dnl_board_usb_cable_connected(void)
+{
+	struct udevice *stusb1600;
+	struct udevice *dwc2_udc_otg;
+	int ret;
+
+	if (!stusb1600_init(&stusb1600))
+		return stusb1600_cable_connected(stusb1600);
+
+	ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
+					  DM_GET_DRIVER(dwc2_udc_otg),
+					  &dwc2_udc_otg);
+	if (!ret)
+		debug("dwc2_udc_otg init failed\n");
+
+	return dwc2_udc_B_session_valid(dwc2_udc_otg);
+}
+#endif /* CONFIG_USB_GADGET */
+
 static int get_led(struct udevice **dev, char *led_string)
 {
 	char *led_name;
@@ -438,16 +361,6 @@
 	return 0;
 }
 
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	/* Reset usbotg */
-	reset_assert(&usbotg_reset);
-	udelay(2);
-	reset_deassert(&usbotg_reset);
-
-	return 0;
-}
-
 static void sysconf_init(void)
 {
 #ifndef CONFIG_STM32MP1_TRUSTED
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 4d6258d..c4e13f8 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -8,9 +8,6 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 obj-y	+= board.o
 obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SUNXI_AHCI)	+= ahci.o
-endif
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun5i_auto.o
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 826650c..d8fdf772 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -12,14 +12,6 @@
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	/* Set up clock gating */
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
-	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
-#else
-	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-#endif
-
 	/* Set MII clock */
 #ifdef CONFIG_RGMII
 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c
index ffa7c15..7c4fcf2 100644
--- a/board/synopsys/axs10x/axs10x.c
+++ b/board/synopsys/axs10x/axs10x.c
@@ -11,35 +11,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_mmc_init(bd_t *bis)
-{
-	struct dwmci_host *host = NULL;
-
-	host = malloc(sizeof(struct dwmci_host));
-	if (!host) {
-		printf("dwmci_host malloc fail!\n");
-		return 1;
-	}
-
-	memset(host, 0, sizeof(struct dwmci_host));
-	host->name = "Synopsys Mobile storage";
-	host->ioaddr = (void *)ARC_DWMMC_BASE;
-	host->buswidth = 4;
-	host->dev_index = 0;
-	host->bus_hz = 50000000;
-
-	add_dwmci(host, host->bus_hz / 2, 400000);
-
-	return 0;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct dwmci_host *host = mmc->priv;
-
-	return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
-}
-
 #define AXS_MB_CREG	0xE0011000
 
 int board_early_init_f(void)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 8a2c201..ac4d980 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -982,6 +982,12 @@
 	 */
 	init_memory_bridge();
 
+	/*
+	 * Switch SDIO external ciu clock divider from default div-by-8 to
+	 * minimum possible div-by-2.
+	 */
+	writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
+
 	return 0;
 }
 
@@ -1019,41 +1025,6 @@
 	return 0;
 }
 
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct dwmci_host *host = mmc->priv;
-
-	return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	struct dwmci_host *host = NULL;
-
-	host = malloc(sizeof(struct dwmci_host));
-	if (!host) {
-		printf("dwmci_host malloc fail!\n");
-		return 1;
-	}
-
-	/*
-	 * Switch SDIO external ciu clock divider from default div-by-8 to
-	 * minimum possible div-by-2.
-	 */
-	writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
-
-	memset(host, 0, sizeof(struct dwmci_host));
-	host->name = "Synopsys Mobile storage";
-	host->ioaddr = (void *)ARC_DWMMC_BASE;
-	host->buswidth = 4;
-	host->dev_index = 0;
-	host->bus_hz = 50000000;
-
-	add_dwmci(host, host->bus_hz / 2, 400000);
-
-	return 0;
-}
-
 int checkboard(void)
 {
 	puts("Board: Synopsys ARC HS Development Kit\n");
diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS
index bf17655..a3ad2f7 100644
--- a/board/tbs/tbs2910/MAINTAINERS
+++ b/board/tbs/tbs2910/MAINTAINERS
@@ -1,6 +1,7 @@
 TBS2910 BOARD
 M:	Soeren Moch <smoch@web.de>
 S:	Maintained
+F:	arch/arm/dts/imx6q-tbs2910.dts
 F:	board/tbs/tbs2910/
 F:	configs/tbs2910_defconfig
 F:	include/configs/tbs2910.h
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index ecb45f2..fb0e773 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -9,9 +9,7 @@
 #include <asm/arch/mx6-pins.h>
 #include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
@@ -22,7 +20,6 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
-#include <i2c.h>
 DECLARE_GLOBAL_DATA_PTR;
 
 #define WEAK_PULLUP	(PAD_CTL_PUS_47K_UP |			\
@@ -33,63 +30,9 @@
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#ifdef CONFIG_SYS_I2C
-/* I2C1, SGTL5000 */
-static struct i2c_pads_info i2c_pad_info0 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
-		.gp = IMX_GPIO_NR(5, 26)
-	}
-};
-
-/* I2C2 HDMI */
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-/* I2C3, CON11, DS1307, PCIe_SMB */
-static struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
-		.gp = IMX_GPIO_NR(1, 6)
-	}
-};
-#endif /* CONFIG_SYS_I2C */
-
 static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -138,6 +81,7 @@
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 
 	/* Reset AR8035 PHY */
+	gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
 	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
 	udelay(500);
 	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
@@ -155,108 +99,6 @@
 }
 
 #ifdef CONFIG_FSL_ESDHC
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__SD2_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__SD2_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__SD2_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__SD2_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__SD2_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__SD2_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__SD4_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__SD4_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC2_BASE_ADDR},
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
-#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	case USDHC4_BASE_ADDR:
-		ret = 1; /* eMMC/uSDHC4 is always present */
-		break;
-	}
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/*
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    SD2
-	 * mmc1                    SD3
-	 * mmc2                    eMMC
-	 */
-	int i, ret;
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			gpio_direction_input(USDHC2_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			gpio_direction_input(USDHC3_CD_GPIO);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-			       "(%d) then supported by the board (%d)\n",
-			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-	return 0;
-}
-
 /* set environment device to boot device when booting from SD */
 int board_mmc_get_env_dev(int devno)
 {
@@ -415,12 +257,6 @@
 };
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-static iomux_v3_cfg_t const usb_otg_pads[] = {
-	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#endif
-
 int board_init(void)
 {
 	/* address of boot parameters */
@@ -429,26 +265,8 @@
 #ifdef CONFIG_VIDEO_IPUV3
 	setup_display();
 #endif
-#ifdef CONFIG_SYS_I2C
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-#endif
-#ifdef CONFIG_DWC_AHSATA
-	setup_sata();
-#endif
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
-#ifdef CONFIG_USB_EHCI_MX6
-	imx_iomux_v3_setup_multiple_pads(
-		usb_otg_pads, ARRAY_SIZE(usb_otg_pads));
-#endif
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: TBS2910 Matrix ARM mini PC\n");
 	return 0;
 }
diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
deleted file mode 100644
index 29d1c31..0000000
--- a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016 Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37
-
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
deleted file mode 100644
index 02e90dd..0000000
--- a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016 Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
-DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46
-
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
index 2c70ab4..7efe816 100644
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -1,9 +1,9 @@
 Apalis iMX6
 M:	Max Krummenacher <max.krummenacher@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
+W:      https://www.toradex.com/community
 S:	Maintained
 F:	board/toradex/apalis_imx6/
 F:	include/configs/apalis_imx6.h
 F:	configs/apalis_imx6_defconfig
-F:	configs/apalis_imx6_nospl_com_defconfig
-F:	configs/apalis_imx6_nospl_it_defconfig
+F:	arch/arm/dts/imx6-apalis.dts
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index d11207c..3e59185 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -2,38 +2,33 @@
 /*
  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  * copied from nitrogen6x
  */
 
 #include <common.h>
 #include <dm.h>
-#include <environment.h>
+
+#include <ahci.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
-#include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mx6-pins.h>
 #include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/bootm.h>
 #include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/video.h>
+#include <dm/device-internal.h>
 #include <dm/platform_data/serial_mxc.h>
-#include <dm/platdata.h>
+#include <dwc_ahsata.h>
+#include <environment.h>
 #include <fsl_esdhc.h>
-#include <i2c.h>
-#include <input.h>
 #include <imx_thermal.h>
-#include <linux/errno.h>
-#include <malloc.h>
-#include <mmc.h>
 #include <micrel.h>
 #include <miiphy.h>
 #include <netdev.h>
@@ -50,40 +45,30 @@
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |		\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
 #define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_SRE_SLOW)
 
-#define NO_PULLUP	(					\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_SRE_SLOW)
-
 #define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 
 #define TRISTATE	(PAD_CTL_HYS | PAD_CTL_SPEED_MED)
 
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
 
+#define APALIS_IMX6_SATA_INIT_RETRIES	10
+
 int dram_init(void)
 {
 	/* use the DDR controllers configured size */
@@ -103,63 +88,7 @@
 	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* Apalis I2C1 */
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
-		.gp = IMX_GPIO_NR(5, 26)
-	}
-};
-
-/* Apalis local, PMIC, SGTL5000, STMPE811 */
-struct i2c_pads_info i2c_pad_info_loc = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-/* Apalis I2C3 / CAM */
-struct i2c_pads_info i2c_pad_info3 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
-		.gp = IMX_GPIO_NR(3, 17)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
-
-/* Apalis I2C2 / DDC */
-struct i2c_pads_info i2c_pad_info_ddc = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
-		.gp = IMX_GPIO_NR(3, 16)
-	}
-};
-
+#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 /* Apalis MMC1 */
 iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -190,18 +119,19 @@
 
 /* eMMC */
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 };
+#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 
 int mx6_rgmii_rework(struct phy_device *phydev)
 {
@@ -241,7 +171,8 @@
 	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	/* KSZ9031 PHY Reset */
-	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL) |
+						  MUX_MODE_SION,
 #	define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 };
 
@@ -253,6 +184,7 @@
 static int reset_enet_phy(struct mii_dev *bus)
 {
 	/* Reset KSZ9031 PHY */
+	gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
 	gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
 	mdelay(10);
 	gpio_set_value(GPIO_ENET_PHY_RESET, 1);
@@ -263,15 +195,24 @@
 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 iomux_v3_cfg_t const gpio_pads[] = {
 	/* Apalis GPIO1 - GPIO8 */
-	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D5__GPIO2_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D7__GPIO2_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLDOWN),
-	MX6_PAD_GPIO_6__GPIO1_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D5__GPIO2_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D7__GPIO2_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_6__GPIO1_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 };
 
 static void setup_iomux_gpio(void)
@@ -281,7 +222,7 @@
 
 iomux_v3_cfg_t const usb_pads[] = {
 	/* USBH_EN */
-	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 #	define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 	/* USB_VBUS_DET */
 	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -289,7 +230,7 @@
 	/* USBO1_ID */
 	MX6_PAD_ENET_RX_ER__USB_OTG_ID	| MUX_PAD_CTRL(WEAK_PULLUP),
 	/* USBO1_EN */
-	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 #	define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 };
 
@@ -297,8 +238,11 @@
  * UARTs are used in DTE mode, switch the mode on all UARTs before
  * any pinmuxing connects a (DCE) output to a transceiver output.
  */
+#define UCR3		0x88	/* FIFO Control Register */
+#define UCR3_RI		BIT(8)	/* RIDELT DTE mode */
+#define UCR3_DCD	BIT(9)	/* DCDDELT DTE mode */
 #define UFCR		0x90	/* FIFO Control Register */
-#define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
+#define UFCR_DCEDTE	BIT(6)	/* DCE=0 */
 
 static void setup_dtemode_uart(void)
 {
@@ -306,6 +250,11 @@
 	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 	setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 	setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
+
+	clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 }
 static void setup_dcemode_uart(void)
 {
@@ -321,7 +270,6 @@
 	imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 					 ARRAY_SIZE(uart1_pads_dte));
 }
-
 static void setup_iomux_dce_uart(void)
 {
 	setup_dcemode_uart();
@@ -335,32 +283,10 @@
 	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 	return 0;
 }
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		/* control OTG power */
-		gpio_direction_output(GPIO_USBO_EN, on);
-		mdelay(100);
-		break;
-	case 1:
-		/* Control MXM USBH */
-		gpio_direction_output(GPIO_USBH_EN, on);
-		mdelay(2);
-		/* Control onboard USB Hub VBUS */
-		gpio_direction_output(GPIO_USB_VBUS_DET, on);
-		mdelay(100);
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
-/* use the following sequence: eMMC, MMC, SD */
+#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
+/* use the following sequence: eMMC, MMC1, SD1 */
 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 	{USDHC3_BASE_ADDR},
 	{USDHC1_BASE_ADDR},
@@ -374,10 +300,12 @@
 
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "MMC_CD");
 		gpio_direction_input(GPIO_MMC_CD);
 		ret = !gpio_get_value(GPIO_MMC_CD);
 		break;
 	case USDHC2_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "SD_CD");
 		gpio_direction_input(GPIO_SD_CD);
 		ret = !gpio_get_value(GPIO_SD_CD);
 		break;
@@ -388,43 +316,6 @@
 
 int board_mmc_init(bd_t *bis)
 {
-#ifndef CONFIG_SPL_BUILD
-	s32 status = 0;
-	u32 index = 0;
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
-	usdhc_cfg[0].max_bus_width = 8;
-	usdhc_cfg[1].max_bus_width = 8;
-	usdhc_cfg[2].max_bus_width = 4;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return status;
-		}
-
-		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-	}
-
-	return status;
-#else
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned reg = readl(&psrc->sbmr1) >> 11;
 	/*
@@ -463,9 +354,8 @@
 	}
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
 }
-#endif
+#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 
 int board_phy_config(struct phy_device *phydev)
 {
@@ -489,6 +379,7 @@
 	bus = fec_get_miibus(base, -1);
 	if (!bus)
 		return 0;
+
 	bus->reset = reset_enet_phy;
 	/* scan PHY 4,5,6,7 */
 	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
@@ -497,6 +388,7 @@
 		puts("no PHY found\n");
 		return 0;
 	}
+
 	printf("using PHY at %d\n", phydev->addr);
 	ret = fec_probe(bis, -1, base, bus, phydev);
 	if (ret) {
@@ -504,7 +396,8 @@
 		free(phydev);
 		free(bus);
 	}
-#endif
+#endif /* CONFIG_FEC_MXC */
+
 	return 0;
 }
 
@@ -520,18 +413,21 @@
 
 static iomux_v3_cfg_t const backlight_pads[] = {
 	/* Backlight on RGB connector: J15 */
-	MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 	/* additional CPU pin on BKL_PWM, keep in tristate */
 	MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 	/* Backlight PWM, used as GPIO in U-Boot */
-	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 	/* buffer output enable 0: buffer enabled */
-	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 	/* PSAVE# integrated VDAC */
-	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 };
 
@@ -571,12 +467,6 @@
 	imx_enable_hdmi_phy();
 }
 
-static int detect_i2c(struct display_info_t const *dev)
-{
-	return (0 == i2c_set_bus_num(dev->bus)) &&
-	       (0 == i2c_probe(dev->addr));
-}
-
 static void enable_lvds(struct display_info_t const *dev)
 {
 	struct iomuxc *iomux = (struct iomuxc *)
@@ -670,7 +560,6 @@
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_LVDS666,
-	.detect	= detect_i2c,
 	.enable	= enable_lvds,
 	.mode	= {
 		.name           = "wsvga-lvds",
@@ -741,6 +630,9 @@
 	imx_iomux_v3_setup_multiple_pads(backlight_pads,
 					 ARRAY_SIZE(backlight_pads));
 	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
+	gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
+	gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
@@ -782,10 +674,6 @@
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
@@ -835,17 +723,18 @@
 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 #endif /* CONFIG_REVISION_TAG */
 
+#ifdef CONFIG_CMD_USB_SDP
+	if (is_boot_from_usb()) {
+		printf("Serial Downloader recovery mode, using sdp command\n");
+		env_set("bootdelay", "0");
+		env_set("bootcmd", "sdp 0");
+	}
+#endif /* CONFIG_CMD_USB_SDP */
+
 	return 0;
 }
 #endif /* CONFIG_BOARD_LATE_INIT */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
-int ft_system_setup(void *blob, bd_t *bd)
-{
-	return 0;
-}
-#endif
-
 int checkboard(void)
 {
 	char it[] = " IT";
@@ -1143,7 +1032,6 @@
 MX6_MMDC_P0_MAPSR, 0x00011006,
 };
 
-
 static void ccgr_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -1204,7 +1092,7 @@
 	ccgr_init();
 	gpr_init();
 
-	/* iomux and setup of i2c */
+	/* iomux */
 	board_early_init_f();
 
 	/* setup GP timer */
@@ -1232,7 +1120,7 @@
 {
 }
 
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 static struct mxc_serial_platdata mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
@@ -1243,3 +1131,52 @@
 	.name = "serial_mxc",
 	.platdata = &mxc_serial_plat,
 };
+
+#if CONFIG_IS_ENABLED(AHCI)
+static int sata_imx_probe(struct udevice *dev)
+{
+	int i, err;
+
+	for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) {
+		err = setup_sata();
+		if (err) {
+			printf("SATA setup failed: %d\n", err);
+			return err;
+		}
+
+		udelay(100);
+
+		err = dwc_ahsata_probe(dev);
+		if (!err)
+			break;
+
+		/* There is no device on the SATA port */
+		if (sata_dm_port_status(0, 0) == 0)
+			break;
+
+		/* There's a device, but link not established. Retry */
+		device_remove(dev, DM_REMOVE_NORMAL);
+	}
+
+	return 0;
+}
+
+struct ahci_ops sata_imx_ops = {
+	.port_status = dwc_ahsata_port_status,
+	.reset	= dwc_ahsata_bus_reset,
+	.scan	= dwc_ahsata_scan,
+};
+
+static const struct udevice_id sata_imx_ids[] = {
+	{ .compatible = "fsl,imx6q-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(sata_imx) = {
+	.name		= "dwc_ahci",
+	.id		= UCLASS_AHCI,
+	.of_match	= sata_imx_ids,
+	.ops		= &sata_imx_ops,
+	.probe		= sata_imx_probe,
+};
+#endif /* AHCI */
diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg
deleted file mode 100644
index 739b1b7..0000000
--- a/board/toradex/apalis_imx6/apalis_imx6q.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-#if CONFIG_DDR_MB == 2048
-#include "1066mhz_4x256mx16.cfg"
-#else
-#include "1066mhz_4x128mx16.cfg"
-#endif
-#include "clocks.cfg"
diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg
deleted file mode 100644
index 1bcbc4f..0000000
--- a/board/toradex/apalis_imx6/clocks.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg
deleted file mode 100644
index e42e3ce..0000000
--- a/board/toradex/apalis_imx6/ddr-setup.cfg
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 32 bits	x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-/*
- * MDSCR	con_req
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c
index e6793e3..22d191f 100644
--- a/board/toradex/apalis_imx6/do_fuse.c
+++ b/board/toradex/apalis_imx6/do_fuse.c
@@ -29,7 +29,7 @@
 		return CMD_RET_FAILURE;
 	}
 	/* boot cfg */
-	fuse_prog(0, 5, 0x00005072);
+	fuse_prog(0, 5, 0x00005062);
 	/* BT_FUSE_SEL */
 	fuse_prog(0, 6, 0x00000010);
 	return CMD_RET_SUCCESS;
diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
index 7334e92..ebd6418 100644
--- a/board/toradex/apalis_imx6/pf0100.c
+++ b/board/toradex/apalis_imx6/pf0100.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  */
 
 /*
@@ -9,7 +9,6 @@
 
 #include <common.h>
 #include <i2c.h>
-#include <linux/compiler.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
@@ -22,6 +21,8 @@
 /* define for PMIC register dump */
 /*#define DEBUG */
 
+#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
+
 /* use Apalis GPIO1 to switch on VPGM, ON: 1 */
 static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
 	MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -30,99 +31,100 @@
 
 unsigned pmic_init(void)
 {
+	int rc;
+	struct udevice *dev = NULL;
 	unsigned programmed = 0;
 	uchar bus = 1;
 	uchar devid, revid, val;
 
-	puts("PMIC: ");
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
+	puts("PMIC:  ");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
 		return 0;
 	}
+
+	/* check for errors in PMIC fuses */
+	if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
+		puts("i2c pmic INTSTAT3 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BIT_OTP_ECCI) {
+		puts("\n" WARNBAR);
+		puts("WARNING: ecc errors found in pmic fuse banks\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE1 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE1) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE2 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE2) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
+		    );
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE1) {
+		puts(WARNBAR);
+		puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE2) {
+		puts(WARNBAR);
+		puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+
 	/* get device ident */
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
 		puts("i2c pmic devid read failed\n");
 		return 0;
 	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
 		puts("i2c pmic revid read failed\n");
 		return 0;
 	}
-	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+	printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
 
-#ifdef DEBUG
-	{
-		unsigned i, j;
-
-		for (i = 0; i < 16; i++)
-			printf("\t%x", i);
-		for (j = 0; j < 0x80; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\nEXT Page 1");
-
-		val = PFUZE100_PAGE_REGISTER_PAGE1;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
-			puts("i2c write failed\n");
-			return 0;
-		}
-
-		for (j = 0x80; j < 0x100; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\nEXT Page 2");
-
-		val = PFUZE100_PAGE_REGISTER_PAGE2;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
-			puts("i2c write failed\n");
-			return 0;
-		}
-
-		for (j = 0x80; j < 0x100; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\n");
-	}
-#endif
 	/* get device programmed state */
 	val = PFUZE100_PAGE_REGISTER_PAGE1;
-	if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
+	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
 		puts("i2c write failed\n");
 		return 0;
 	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return 0;
 	}
 	if (val & PFUZE100_FUSE_POR_M)
 		programmed++;
 
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return programmed;
 	}
 	if (val & PFUZE100_FUSE_POR_M)
 		programmed++;
 
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return programmed;
 	}
@@ -131,13 +133,13 @@
 
 	switch (programmed) {
 	case 0:
-		printf("PMIC: not programmed\n");
+		puts("not programmed\n");
 		break;
 	case 3:
-		printf("PMIC: programmed\n");
+		puts("programmed\n");
 		break;
 	default:
-		printf("PMIC: undefined programming state\n");
+		puts("undefined programming state\n");
 		break;
 	}
 
@@ -145,25 +147,75 @@
 	if (programmed != 3) {
 		/* set VGEN1 to 1.2V */
 		val = PFUZE100_VGEN1_VAL;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1,
-			      &val, 1)) {
+		if (dm_i2c_write(dev, PFUZE100_VGEN1CTL, &val, 1)) {
 			puts("i2c write failed\n");
 			return programmed;
 		}
 
 		/* set SWBST to 5.0V */
 		val = PFUZE100_SWBST_VAL;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1,
-			      &val, 1)) {
+		if (dm_i2c_write(dev, PFUZE100_SWBSTCTL, &val, 1))
 			puts("i2c write failed\n");
-		}
 	}
+
+#ifdef DEBUG
+	{
+		unsigned int i, j;
+
+		for (i = 0; i < 16; i++)
+			printf("\t%x", i);
+		for (j = 0; j < 0x80; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 1");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE1;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 2");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE2;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\n");
+	}
+#endif /* DEBUG */
+
 	return programmed;
 }
 
 #ifndef CONFIG_SPL_BUILD
 static int pf0100_prog(void)
 {
+	int rc;
+	struct udevice *dev = NULL;
 	unsigned char bus = 1;
 	unsigned char val;
 	unsigned int i;
@@ -177,9 +229,10 @@
 					 ARRAY_SIZE(pmic_prog_pads));
 	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
 
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
 		return CMD_RET_FAILURE;
 	}
 
@@ -187,8 +240,7 @@
 		switch (pmic_otp_prog[i].cmd) {
 		case pmic_i2c:
 			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
-			if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
-				      1, &val, 1)) {
+			if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
 				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
 				       pmic_otp_prog[i].reg, val);
 				return CMD_RET_FAILURE;
@@ -227,4 +279,4 @@
 	"Program the OTP fuses on the PMIC PF0100",
 	""
 );
-#endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h
index c0efb79..9257620 100644
--- a/board/toradex/apalis_imx6/pf0100.h
+++ b/board/toradex/apalis_imx6/pf0100.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  */
 
 /*
@@ -10,11 +10,23 @@
 #ifndef PF0100_H_
 #define PF0100_H_
 
+/* bit definitions */
+#define PFUZE100_BIT_0			(0x01 << 0)
+#define PFUZE100_BIT_1			(0x01 << 1)
+#define PFUZE100_BIT_2			(0x01 << 2)
+#define PFUZE100_BIT_3			(0x01 << 3)
+#define PFUZE100_BIT_4			(0x01 << 4)
+#define PFUZE100_BIT_5			(0x01 << 5)
+#define PFUZE100_BIT_6			(0x01 << 6)
+#define PFUZE100_BIT_7			(0x01 << 7)
+
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR		(0x08)
 /* Register Addresses */
 #define PFUZE100_DEVICEID		(0x0)
 #define PFUZE100_REVID			(0x3)
+#define PFUZE100_INTSTAT3		(0xe)
+#define PFUZE100_BIT_OTP_ECCI		PFUZE100_BIT_7
 #define PFUZE100_SW1AMODE		(0x23)
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
@@ -39,12 +51,55 @@
 #define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
 
 /* extended page 1 */
+#define PFUZE100_OTP_ECC_SE1		0x8a
+#define PFUZE100_BIT_ECC1_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE1		((PFUZE100_BIT_ECC1_SE) | \
+					(PFUZE100_BIT_ECC2_SE) | \
+					(PFUZE100_BIT_ECC3_SE) | \
+					(PFUZE100_BIT_ECC4_SE) | \
+					(PFUZE100_BIT_ECC5_SE))
+#define PFUZE100_OTP_ECC_SE2		0x8b
+#define PFUZE100_BIT_ECC6_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE2		((PFUZE100_BIT_ECC6_SE) | \
+					(PFUZE100_BIT_ECC7_SE) | \
+					(PFUZE100_BIT_ECC8_SE) | \
+					(PFUZE100_BIT_ECC9_SE) | \
+					(PFUZE100_BIT_ECC10_SE))
+#define PFUZE100_OTP_ECC_DE1		0x8c
+#define PFUZE100_BIT_ECC1_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE1		((PFUZE100_BIT_ECC1_DE) | \
+					(PFUZE100_BIT_ECC2_DE) | \
+					(PFUZE100_BIT_ECC3_DE) | \
+					(PFUZE100_BIT_ECC4_DE) | \
+					(PFUZE100_BIT_ECC5_DE))
+#define PFUZE100_OTP_ECC_DE2		0x8d
+#define PFUZE100_BIT_ECC6_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE2		((PFUZE100_BIT_ECC6_DE) | \
+					(PFUZE100_BIT_ECC7_DE) | \
+					(PFUZE100_BIT_ECC8_DE) | \
+					(PFUZE100_BIT_ECC9_DE) | \
+					(PFUZE100_BIT_ECC10_DE))
 #define PFUZE100_FUSE_POR1		0xe4
 #define PFUZE100_FUSE_POR2		0xe5
 #define PFUZE100_FUSE_POR3		0xe6
 #define PFUZE100_FUSE_POR_M		(0x1 << 1)
 
-
 /* output some informational messages, return the number FUSE_POR=1 */
 /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
 unsigned pmic_init(void);
diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
deleted file mode 100644
index c940714..0000000
--- a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-/* DDR3 DATA BUS SIZE: 64BIT */
-/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */
-/* DDR3 DATA BUS SIZE: 32BIT */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000
-
-/* Write commands to DDR */
-/* Load Mode Registers */
-/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
-/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
deleted file mode 100644
index c319d2a..0000000
--- a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-/* DDR3 DATA BUS SIZE: 64BIT */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000
-/* DDR3 DATA BUS SIZE: 32BIT */
-/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */
-
-/* Write commands to DDR */
-/* Load Mode Registers */
-/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
-/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
index 1cc7ef2..e25c073 100644
--- a/board/toradex/colibri_imx6/MAINTAINERS
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -1,8 +1,9 @@
 Colibri iMX6
 M:	Max Krummenacher <max.krummenacher@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
+W:      https://www.toradex.com/community
 S:	Maintained
 F:	board/toradex/colibri_imx6/
 F:	include/configs/colibri_imx6.h
 F:	configs/colibri_imx6_defconfig
-F:	configs/colibri_imx6_nospl_defconfig
+F:	arch/arm/dts/imx6-colibri.dts
diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg
deleted file mode 100644
index 1bcbc4f..0000000
--- a/board/toradex/colibri_imx6/clocks.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 17876f2..c634e32 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -2,40 +2,35 @@
 /*
  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  * copied from nitrogen6x
  */
 
 #include <common.h>
 #include <dm.h>
+
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
 #include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/bootm.h>
 #include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/video.h>
-#include <asm/io.h>
+#include <cpu.h>
 #include <dm/platform_data/serial_mxc.h>
-#include <dm/platdata.h>
+#include <environment.h>
 #include <fsl_esdhc.h>
-#include <i2c.h>
-#include <input.h>
 #include <imx_thermal.h>
-#include <linux/errno.h>
-#include <malloc.h>
 #include <micrel.h>
 #include <miiphy.h>
-#include <mmc.h>
 #include <netdev.h>
+#include <cpu.h>
 
 #include "../common/tdx-cfg-block.h"
 #ifdef CONFIG_TDX_CMD_IMX_MFGR
@@ -49,22 +44,16 @@
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |		\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
 #define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_SRE_SLOW)
@@ -77,8 +66,6 @@
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
 
 int dram_init(void)
@@ -96,36 +83,8 @@
 	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* Colibri I2C */
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
-		.gp = IMX_GPIO_NR(1, 6)
-	}
-};
-
-/* Colibri local, PMIC, SGTL5000, STMPE811 */
-struct i2c_pads_info i2c_pad_info_loc = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
-		.gp = IMX_GPIO_NR(3, 16)
-	}
-};
-
-/* Apalis MMC */
+#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
+/* Colibri MMC */
 iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -139,18 +98,19 @@
 
 /* eMMC */
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
+#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -173,68 +133,123 @@
 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 iomux_v3_cfg_t const gpio_pads[] = {
 	/* ADDRESS[17:18] [25] used as GPIO */
-	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_KEY_COL2__GPIO4_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D1__GPIO2_IO01	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_KEY_COL2__GPIO4_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D1__GPIO2_IO01	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* ADDRESS[19:24] used as GPIO */
-	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* DATA[16:29] [31]	 used as GPIO */
-	MX6_PAD_EIM_LBA__GPIO2_IO27	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_ALE__GPIO6_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CS0__GPIO6_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CLE__GPIO6_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_LBA__GPIO2_IO27	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_ALE__GPIO6_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS0__GPIO6_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CLE__GPIO6_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* DQM[0:3]	 used as GPIO */
-	MX6_PAD_EIM_EB0__GPIO2_IO28	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_EB1__GPIO2_IO29	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD2_DAT2__GPIO1_IO13	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D0__GPIO2_IO00	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_EB0__GPIO2_IO28	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_EB1__GPIO2_IO29	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_DAT2__GPIO1_IO13	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D0__GPIO2_IO00	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* RDY	used as GPIO */
-	MX6_PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* ADDRESS[16] DATA[30]	 used as GPIO */
-	MX6_PAD_KEY_ROW4__GPIO4_IO15	| MUX_PAD_CTRL(WEAK_PULLDOWN),
-	MX6_PAD_KEY_COL4__GPIO4_IO14	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_KEY_ROW4__GPIO4_IO15	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_KEY_COL4__GPIO4_IO14	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* CSI pins used as GPIO */
-	MX6_PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD2_CMD__GPIO1_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_D18__GPIO3_IO18	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_D29__GPIO3_IO29	| MUX_PAD_CTRL(WEAK_PULLDOWN),
-	MX6_PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_A20__GPIO2_IO18	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_EB3__GPIO2_IO31	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_CMD__GPIO1_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D18__GPIO3_IO18	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D29__GPIO3_IO29	| MUX_PAD_CTRL(WEAK_PULLDOWN) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A20__GPIO2_IO18	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_EB3__GPIO2_IO31	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* GPIO */
-	MX6_PAD_EIM_D26__GPIO3_IO26	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D3__GPIO2_IO03	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD4_DAT3__GPIO2_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_SD4_DAT0__GPIO2_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_8__GPIO1_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_D26__GPIO3_IO26	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D3__GPIO2_IO03	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD4_DAT3__GPIO2_IO11	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_SD4_DAT0__GPIO2_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
+	MX6_PAD_GPIO_8__GPIO1_IO08	| MUX_PAD_CTRL(WEAK_PULLUP) |
+					  MUX_MODE_SION,
 	/* USBH_OC */
 	MX6_PAD_EIM_D30__GPIO3_IO30	| MUX_PAD_CTRL(WEAK_PULLUP),
 	/* USBC_ID */
@@ -249,8 +264,8 @@
 }
 
 iomux_v3_cfg_t const usb_pads[] = {
-	/* USB_PE */
-	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* USBH_PEN */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 #	define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 };
 
@@ -258,14 +273,21 @@
  * UARTs are used in DTE mode, switch the mode on all UARTs before
  * any pinmuxing connects a (DCE) output to a transceiver output.
  */
+#define UCR3		0x88	/* FIFO Control Register */
+#define UCR3_RI		BIT(8)	/* RIDELT DTE mode */
+#define UCR3_DCD	BIT(9)	/* DCDDELT DTE mode */
 #define UFCR		0x90	/* FIFO Control Register */
-#define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
+#define UFCR_DCEDTE	BIT(6)	/* DCE=0 */
 
 static void setup_dtemode_uart(void)
 {
 	setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 	setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
+
+	clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
+	clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
 }
 
 static void setup_iomux_uart(void)
@@ -280,29 +302,9 @@
 	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 	return 0;
 }
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		/* control OTG power */
-		/* No special PE for USBC, always on when ID pin signals
-		   host mode */
-		break;
-	case 1:
-		/* Control MXM USBH */
-		/* Set MXM USBH power enable, '0' means on */
-		gpio_direction_output(GPIO_USBH_EN, !on);
-		mdelay(100);
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 /* use the following sequence: eMMC, MMC */
 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 	{USDHC3_BASE_ADDR},
@@ -316,6 +318,7 @@
 
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
+		gpio_request(GPIO_MMC_CD, "MMC_CD");
 		gpio_direction_input(GPIO_MMC_CD);
 		ret = !gpio_get_value(GPIO_MMC_CD);
 		break;
@@ -326,37 +329,6 @@
 
 int board_mmc_init(bd_t *bis)
 {
-#ifndef CONFIG_SPL_BUILD
-	s32 status = 0;
-	u32 index = 0;
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	usdhc_cfg[0].max_bus_width = 8;
-	usdhc_cfg[1].max_bus_width = 4;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return status;
-		}
-
-		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-	}
-
-	return status;
-#else
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned reg = readl(&psrc->sbmr1) >> 11;
 	/*
@@ -388,9 +360,8 @@
 	}
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
 }
-#endif
+#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 
 int board_phy_config(struct phy_device *phydev)
 {
@@ -412,6 +383,7 @@
 	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 	if (ret)
 		return ret;
+
 	/* set gpr1[ENET_CLK_SEL] */
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 
@@ -421,6 +393,7 @@
 	bus = fec_get_miibus(base, -1);
 	if (!bus)
 		return 0;
+
 	/* scan PHY 1..7 */
 	phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
 	if (!phydev) {
@@ -428,6 +401,7 @@
 		puts("no PHY found\n");
 		return 0;
 	}
+
 	phy_reset(phydev);
 	printf("using PHY at %d\n", phydev->addr);
 	ret = fec_probe(bis, -1, base, bus, phydev);
@@ -436,7 +410,8 @@
 		free(phydev);
 		free(bus);
 	}
-#endif
+#endif /* CONFIG_FEC_MXC */
+
 	return 0;
 }
 
@@ -452,11 +427,12 @@
 
 static iomux_v3_cfg_t const backlight_pads[] = {
 	/* Backlight On */
-	MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 	/* Backlight PWM, used as GPIO in U-Boot */
 	MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
-	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+				       MUX_MODE_SION,
 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 };
 
@@ -619,6 +595,8 @@
 	imx_iomux_v3_setup_multiple_pads(backlight_pads,
 					 ARRAY_SIZE(backlight_pads));
 	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
+	gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 }
@@ -656,9 +634,6 @@
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
-
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
@@ -689,17 +664,18 @@
 	env_set("board_rev", env_str);
 #endif
 
+#ifdef CONFIG_CMD_USB_SDP
+	if (is_boot_from_usb()) {
+		printf("Serial Downloader recovery mode, using sdp command\n");
+		env_set("bootdelay", "0");
+		env_set("bootcmd", "sdp 0");
+	}
+#endif /* CONFIG_CMD_USB_SDP */
+
 	return 0;
 }
 #endif /* CONFIG_BOARD_LATE_INIT */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
-int ft_system_setup(void *blob, bd_t *bd)
-{
-	return 0;
-}
-#endif
-
 int checkboard(void)
 {
 	char it[] = " IT";
@@ -722,7 +698,18 @@
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	return ft_common_board_setup(blob, bd);
+	u32 cma_size;
+
+	ft_common_board_setup(blob, bd);
+
+	cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
+	cma_size = min((u32)(gd->ram_size >> 1), cma_size);
+
+	fdt_setprop_u32(blob,
+			fdt_path_offset(blob, "/reserved-memory/linux,cma"),
+			"size",
+			cma_size);
+	return 0;
 }
 #endif
 
@@ -1073,6 +1060,7 @@
 	case TEMP_AUTOMOTIVE:
 	default:
 		if (is_cpu_type(MXC_CPU_MX6DL)) {
+			puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
 			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
 		} else {
 			puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
@@ -1083,6 +1071,26 @@
 	udelay(100);
 }
 
+static iomux_v3_cfg_t const gpio_reset_pad[] = {
+	MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+					MUX_MODE_SION
+#define GPIO_NRESET IMX_GPIO_NR(6, 27)
+};
+
+#define IMX_RESET_CAUSE_POR 0x00011
+static void nreset_out(void)
+{
+	int reset_cause = get_imx_reset_cause();
+
+	if (reset_cause != IMX_RESET_CAUSE_POR) {
+		imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
+						 ARRAY_SIZE(gpio_reset_pad));
+		gpio_direction_output(GPIO_NRESET, 1);
+		udelay(100);
+		gpio_direction_output(GPIO_NRESET, 0);
+	}
+}
+
 void board_init_f(ulong dummy)
 {
 	/* setup AIPS and disable watchdog */
@@ -1091,7 +1099,7 @@
 	ccgr_init();
 	gpr_init();
 
-	/* iomux and setup of i2c */
+	/* iomux */
 	board_early_init_f();
 
 	/* setup GP timer */
@@ -1109,6 +1117,9 @@
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
+	/* Assert nReset_Out */
+	nreset_out();
+
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
@@ -1117,7 +1128,7 @@
 {
 }
 
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 static struct mxc_serial_platdata mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART1_BASE,
diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg
deleted file mode 100644
index 517c5eb..0000000
--- a/board/toradex/colibri_imx6/colibri_imx6.cfg
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014 Toradex AG
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-
-#if CONFIG_DDR_MB == 256
-#include "800mhz_2x64mx16.cfg"
-#elif CONFIG_DDR_MB == 512
-#include "800mhz_4x64mx16.cfg"
-#else
-#error "unknown DDR size"
-#endif
-
-#include "clocks.cfg"
diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg
deleted file mode 100644
index a943fd2..0000000
--- a/board/toradex/colibri_imx6/ddr-setup.cfg
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 32 bits	x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-/* TODO: check what the RALAT field does */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-/*
- * MDSCR	con_req
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c
index e6793e3..22d191f 100644
--- a/board/toradex/colibri_imx6/do_fuse.c
+++ b/board/toradex/colibri_imx6/do_fuse.c
@@ -29,7 +29,7 @@
 		return CMD_RET_FAILURE;
 	}
 	/* boot cfg */
-	fuse_prog(0, 5, 0x00005072);
+	fuse_prog(0, 5, 0x00005062);
 	/* BT_FUSE_SEL */
 	fuse_prog(0, 6, 0x00000010);
 	return CMD_RET_SUCCESS;
diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c
index fa63865..e744243 100644
--- a/board/toradex/colibri_imx6/pf0100.c
+++ b/board/toradex/colibri_imx6/pf0100.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  */
 
 /*
@@ -21,6 +21,8 @@
 /* define for PMIC register dump */
 /*#define DEBUG */
 
+#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
+
 /* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
 static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
 	MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -29,99 +31,100 @@
 
 unsigned pmic_init(void)
 {
+	int rc;
+	struct udevice *dev = NULL;
 	unsigned programmed = 0;
 	uchar bus = 1;
 	uchar devid, revid, val;
 
-	puts("PMIC: ");
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
+	puts("PMIC:  ");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
 		return 0;
 	}
+
+	/* check for errors in PMIC fuses */
+	if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
+		puts("i2c pmic INTSTAT3 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BIT_OTP_ECCI) {
+		puts("\n" WARNBAR);
+		puts("WARNING: ecc errors found in pmic fuse banks\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE1 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE1) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_SE2 register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_SE2) {
+		puts(WARNBAR);
+		puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
+		    );
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE1) {
+		puts(WARNBAR);
+		puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+	if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
+		puts("i2c pmic ECC_DE register read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_BITS_ECC_DE2) {
+		puts(WARNBAR);
+		puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
+		puts(WARNBAR);
+	}
+
 	/* get device ident */
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
 		puts("i2c pmic devid read failed\n");
 		return 0;
 	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
 		puts("i2c pmic revid read failed\n");
 		return 0;
 	}
-	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+	printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
 
-#ifdef DEBUG
-	{
-		unsigned i, j;
-
-		for (i = 0; i < 16; i++)
-			printf("\t%x", i);
-		for (j = 0; j < 0x80; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\nEXT Page 1");
-
-		val = PFUZE100_PAGE_REGISTER_PAGE1;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
-			puts("i2c write failed\n");
-			return 0;
-		}
-
-		for (j = 0x80; j < 0x100; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\nEXT Page 2");
-
-		val = PFUZE100_PAGE_REGISTER_PAGE2;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
-			puts("i2c write failed\n");
-			return 0;
-		}
-
-		for (j = 0x80; j < 0x100; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\n");
-	}
-#endif
 	/* get device programmed state */
 	val = PFUZE100_PAGE_REGISTER_PAGE1;
-	if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
+	if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
 		puts("i2c write failed\n");
 		return 0;
 	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return 0;
 	}
 	if (val & PFUZE100_FUSE_POR_M)
 		programmed++;
 
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return programmed;
 	}
 	if (val & PFUZE100_FUSE_POR_M)
 		programmed++;
 
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
+	if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
 		puts("i2c fuse_por read failed\n");
 		return programmed;
 	}
@@ -130,22 +133,74 @@
 
 	switch (programmed) {
 	case 0:
-		printf("PMIC: not programmed\n");
+		puts("not programmed\n");
 		break;
 	case 3:
-		printf("PMIC: programmed\n");
+		puts("programmed\n");
 		break;
 	default:
-		printf("PMIC: undefined programming state\n");
+		puts("undefined programming state\n");
 		break;
 	}
 
+#ifdef DEBUG
+	{
+		unsigned int i, j;
+
+		for (i = 0; i < 16; i++)
+			printf("\t%x", i);
+		for (j = 0; j < 0x80; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 1");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE1;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 2");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE2;
+		if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				dm_i2c_read(dev, j + i, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\n");
+	}
+#endif /* DEBUG */
+
 	return programmed;
 }
 
 #ifndef CONFIG_SPL_BUILD
 static int pf0100_prog(void)
 {
+	int rc;
+	struct udevice *dev = NULL;
 	unsigned char bus = 1;
 	unsigned char val;
 	unsigned int i;
@@ -159,9 +214,10 @@
 					 ARRAY_SIZE(pmic_prog_pads));
 	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
 
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
+	rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
+	if (rc) {
+		printf("failed to get device for PMIC at address 0x%x\n",
+		       PFUZE100_I2C_ADDR);
 		return CMD_RET_FAILURE;
 	}
 
@@ -169,8 +225,7 @@
 		switch (pmic_otp_prog[i].cmd) {
 		case pmic_i2c:
 			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
-			if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
-				      1, &val, 1)) {
+			if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
 				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
 				       pmic_otp_prog[i].reg, val);
 				return CMD_RET_FAILURE;
@@ -209,4 +264,4 @@
 	"Program the OTP fuses on the PMIC PF0100",
 	""
 );
-#endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h
index c0efb79..9257620 100644
--- a/board/toradex/colibri_imx6/pf0100.h
+++ b/board/toradex/colibri_imx6/pf0100.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014-2016, Toradex AG
+ * Copyright (C) 2014-2019, Toradex AG
  */
 
 /*
@@ -10,11 +10,23 @@
 #ifndef PF0100_H_
 #define PF0100_H_
 
+/* bit definitions */
+#define PFUZE100_BIT_0			(0x01 << 0)
+#define PFUZE100_BIT_1			(0x01 << 1)
+#define PFUZE100_BIT_2			(0x01 << 2)
+#define PFUZE100_BIT_3			(0x01 << 3)
+#define PFUZE100_BIT_4			(0x01 << 4)
+#define PFUZE100_BIT_5			(0x01 << 5)
+#define PFUZE100_BIT_6			(0x01 << 6)
+#define PFUZE100_BIT_7			(0x01 << 7)
+
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR		(0x08)
 /* Register Addresses */
 #define PFUZE100_DEVICEID		(0x0)
 #define PFUZE100_REVID			(0x3)
+#define PFUZE100_INTSTAT3		(0xe)
+#define PFUZE100_BIT_OTP_ECCI		PFUZE100_BIT_7
 #define PFUZE100_SW1AMODE		(0x23)
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
@@ -39,12 +51,55 @@
 #define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
 
 /* extended page 1 */
+#define PFUZE100_OTP_ECC_SE1		0x8a
+#define PFUZE100_BIT_ECC1_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE1		((PFUZE100_BIT_ECC1_SE) | \
+					(PFUZE100_BIT_ECC2_SE) | \
+					(PFUZE100_BIT_ECC3_SE) | \
+					(PFUZE100_BIT_ECC4_SE) | \
+					(PFUZE100_BIT_ECC5_SE))
+#define PFUZE100_OTP_ECC_SE2		0x8b
+#define PFUZE100_BIT_ECC6_SE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_SE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_SE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_SE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_SE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_SE2		((PFUZE100_BIT_ECC6_SE) | \
+					(PFUZE100_BIT_ECC7_SE) | \
+					(PFUZE100_BIT_ECC8_SE) | \
+					(PFUZE100_BIT_ECC9_SE) | \
+					(PFUZE100_BIT_ECC10_SE))
+#define PFUZE100_OTP_ECC_DE1		0x8c
+#define PFUZE100_BIT_ECC1_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC2_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC3_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC4_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC5_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE1		((PFUZE100_BIT_ECC1_DE) | \
+					(PFUZE100_BIT_ECC2_DE) | \
+					(PFUZE100_BIT_ECC3_DE) | \
+					(PFUZE100_BIT_ECC4_DE) | \
+					(PFUZE100_BIT_ECC5_DE))
+#define PFUZE100_OTP_ECC_DE2		0x8d
+#define PFUZE100_BIT_ECC6_DE		PFUZE100_BIT_0
+#define PFUZE100_BIT_ECC7_DE		PFUZE100_BIT_1
+#define PFUZE100_BIT_ECC8_DE		PFUZE100_BIT_2
+#define PFUZE100_BIT_ECC9_DE		PFUZE100_BIT_3
+#define PFUZE100_BIT_ECC10_DE		PFUZE100_BIT_4
+#define PFUZE100_BITS_ECC_DE2		((PFUZE100_BIT_ECC6_DE) | \
+					(PFUZE100_BIT_ECC7_DE) | \
+					(PFUZE100_BIT_ECC8_DE) | \
+					(PFUZE100_BIT_ECC9_DE) | \
+					(PFUZE100_BIT_ECC10_DE))
 #define PFUZE100_FUSE_POR1		0xe4
 #define PFUZE100_FUSE_POR2		0xe5
 #define PFUZE100_FUSE_POR3		0xe6
 #define PFUZE100_FUSE_POR_M		(0x1 << 1)
 
-
 /* output some informational messages, return the number FUSE_POR=1 */
 /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
 unsigned pmic_init(void);
diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc
index ce29b95..c3b1f67 100644
--- a/board/toradex/colibri_imx6/pf0100_otp.inc
+++ b/board/toradex/colibri_imx6/pf0100_otp.inc
@@ -5,16 +5,17 @@
 
 // Register Output for PF0100 programmer
 // Customer: Toradex AG
-// Program: Colibri iMX6
+// Program: Colibri iMX6 V1.1
 // Sample marking:
-// Date: 24.07.2015
-// Time: 10:52:58
+// Date: 01.05.2017
+// Time: 16:22:32
 // Generated from Spreadsheet Revision: P1.8
 
-/* sed commands to get from programmer script to struct */
+/* sed commands to get from programmer script to struct content */
 /* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
    sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
-   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc
+*/
 
 enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
 struct pmic_otp_prog_t{
@@ -47,7 +48,8 @@
 {pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
 {pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
 {pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
-{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
+{pmic_i2c, 0xD0, 0x0F}, // Auto gen from Row142
+{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
 {pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
 {pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
 {pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
@@ -185,4 +187,4 @@
 {pmic_delay, 0, 500},
 {pmic_pwr, 0, 1},
 #endif
-};
\ No newline at end of file
+};
diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
index a1217a4..3ee2b33 100644
--- a/board/toradex/colibri_vf/MAINTAINERS
+++ b/board/toradex/colibri_vf/MAINTAINERS
@@ -1,10 +1,12 @@
 Colibri VFxx
 M:	Stefan Agner <stefan.agner@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+W:      https://www.toradex.com/community
 S:	Maintained
 F:	board/toradex/colibri_vf/
 F:	include/configs/colibri_vf.h
 F:	configs/colibri_vf_defconfig
-F:	configs/colibri_vf_dtb_defconfig
 F:	arch/arm/dts/vf-colibri.dtsi
+F:	arch/arm/dts/vf-colibri-u-boot.dtsi
 F:	arch/arm/dts/vf500-colibri.dts
 F:	arch/arm/dts/vf610-colibri.dts
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 79f702f..9d63fbf 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -1,48 +1,41 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2015 Toradex, Inc.
+ * Copyright 2015-2019 Toradex, Inc.
  *
  * Based on vf610twr.c:
  * Copyright 2013 Freescale Semiconductor, Inc.
  */
 
 #include <common.h>
-#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/ddrmc-vf610.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux-vf610.h>
-#include <asm/arch/ddrmc-vf610.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <mmc.h>
-#include <fdt_support.h>
-#include <fsl_esdhc.h>
-#include <fsl_dcu_fb.h>
-#include <jffs2/load_kernel.h>
-#include <miiphy.h>
-#include <mtd_node.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <g_dnl.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <fsl_dcu_fb.h>
+#include <g_dnl.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
 #include <usb.h>
+
 #include "../common/tdx-common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
-			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
-			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-#define USB_PEN_GPIO		83
-#define USB_CDET_GPIO		102
 #define PTC0_GPIO_45		45
 
 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
+	{ DDRMC_CR79_CTLUPD_AREF(1), 79 },
+	/* sets manual values for read lvl. (gate) delay of data slice 0/1 */
+	{ DDRMC_CR105_RDLVL_DL_0(28), 105 },
+	{ DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
+	{ DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
+	{ DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
+
 	/* AXI */
 	{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
 	{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
@@ -89,11 +82,6 @@
 	{ 0, -1 }
 };
 
-static const iomux_v3_cfg_t usb_pads[] = {
-	VF610_PAD_PTD4__GPIO_83,
-	VF610_PAD_PTC29__GPIO_102,
-};
-
 int dram_init(void)
 {
 	static const struct ddr3_jedec_timings timings = {
@@ -120,15 +108,21 @@
 		.tras_lockout      = 0,
 		.tdal              = 12,
 		.bstlen            = 3,
-		.tdll              = 512,
+		.tdll              = 512, /* not applicable since freq. scaling
+					   * is not used
+					   */
 		.trp_ab            = 6,
 		.tref              = 3120,
 		.trfc              = 64,
 		.tref_int          = 0,
 		.tpdex             = 3,
 		.txpdll            = 10,
-		.txsnr             = 48,
-		.txsr              = 468,
+		.txsnr             = 68,  /* changed to conform to JEDEC
+					   * specifications
+					   */
+		.txsr              = 506, /* changed to conform to JEDEC
+					   * specifications
+					   */
 		.cksrx             = 5,
 		.cksre             = 5,
 		.freq_chg_en       = 0,
@@ -147,92 +141,12 @@
 		.wldqsen           = 25,
 	};
 
-	ddrmc_setup_iomux(NULL, 0);
-
 	ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 
 	return 0;
 }
 
-static void setup_iomux_uart(void)
-{
-	static const iomux_v3_cfg_t uart_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-static void setup_iomux_enet(void)
-{
-	static const iomux_v3_cfg_t enet0_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
-}
-
-static void setup_iomux_i2c(void)
-{
-	static const iomux_v3_cfg_t i2c0_pads[] = {
-		VF610_PAD_PTB14__I2C0_SCL,
-		VF610_PAD_PTB15__I2C0_SDA,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
-}
-
-#ifdef CONFIG_NAND_VF610_NFC
-static void setup_iomux_nfc(void)
-{
-	static const iomux_v3_cfg_t nfc_pads[] = {
-		VF610_PAD_PTD23__NF_IO7,
-		VF610_PAD_PTD22__NF_IO6,
-		VF610_PAD_PTD21__NF_IO5,
-		VF610_PAD_PTD20__NF_IO4,
-		VF610_PAD_PTD19__NF_IO3,
-		VF610_PAD_PTD18__NF_IO2,
-		VF610_PAD_PTD17__NF_IO1,
-		VF610_PAD_PTD16__NF_IO0,
-		VF610_PAD_PTB24__NF_WE_B,
-		VF610_PAD_PTB25__NF_CE0_B,
-		VF610_PAD_PTB27__NF_RE_B,
-		VF610_PAD_PTC26__NF_RB_B,
-		VF610_PAD_PTC27__NF_ALE,
-		VF610_PAD_PTC28__NF_CLE
-	};
-
-	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
-}
-#endif
-
-#ifdef CONFIG_FSL_DSPI
-static void setup_iomux_dspi(void)
-{
-	static const iomux_v3_cfg_t dspi1_pads[] = {
-		VF610_PAD_PTD5__DSPI1_CS0,
-		VF610_PAD_PTD6__DSPI1_SIN,
-		VF610_PAD_PTD7__DSPI1_SOUT,
-		VF610_PAD_PTD8__DSPI1_SCK,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
-}
-#endif
-
 #ifdef CONFIG_VYBRID_GPIO
 static void setup_iomux_gpio(void)
 {
@@ -331,37 +245,6 @@
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
-	{ESDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	/* eSDHC1 is always present */
-	return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	static const iomux_v3_cfg_t esdhc1_pads[] = {
-		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
-		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
-	};
-
-	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	imx_iomux_v3_setup_multiple_pads(
-		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
-
-	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
 static inline int is_colibri_vf61(void)
 {
 	struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
@@ -394,7 +277,7 @@
 			CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 			CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
-			CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
+			CCM_CCGR4_GPC_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 			CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
@@ -483,34 +366,15 @@
 		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 }
 
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 int board_early_init_f(void)
 {
 	clock_init();
 	mscm_init();
 
-	setup_iomux_uart();
-	setup_iomux_enet();
-	setup_iomux_i2c();
-#ifdef CONFIG_NAND_VF610_NFC
-	setup_iomux_nfc();
-#endif
-
 #ifdef CONFIG_VYBRID_GPIO
 	setup_iomux_gpio();
 #endif
 
-#ifdef CONFIG_FSL_DSPI
-	setup_iomux_dspi();
-#endif
-
 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 	setup_tcon();
 	setup_iomux_fsl_dcu();
@@ -548,22 +412,17 @@
 	 * so we must use the external oscillator in order
 	 * to maintain correct time in the hwclock
 	 */
-
 	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
 
-#ifdef CONFIG_USB_EHCI_VF
-	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
-#endif
-
 	return 0;
 }
 
 int checkboard(void)
 {
 	if (is_colibri_vf61())
-		puts("Board: Colibri VF61\n");
+		puts("Model: Toradex Colibri VF61\n");
 	else
-		puts("Board: Colibri VF50\n");
+		puts("Model: Toradex Colibri VF50\n");
 
 	return 0;
 }
@@ -591,49 +450,6 @@
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI_VF
-int board_ehci_hcd_init(int port)
-{
-	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
-
-	switch (port) {
-	case 0:
-		/* USBC does not have PEN, also configured as USB client only */
-		break;
-	case 1:
-		gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
-		gpio_direction_output(USB_PEN_GPIO, 0);
-		break;
-	}
-	return 0;
-}
-
-int board_usb_phy_mode(int port)
-{
-	switch (port) {
-	case 0:
-		/*
-		 * Port 0 is used only in client mode on Colibri Vybrid modules
-		 * Check for state of USB client gpio pin and accordingly return
-		 * USB_INIT_DEVICE or USB_INIT_HOST.
-		 */
-		if (gpio_get_value(USB_CDET_GPIO))
-			return USB_INIT_DEVICE;
-		else
-			return USB_INIT_HOST;
-	case 1:
-		/* Port 1 is used only in host mode on Colibri Vybrid modules */
-		return USB_INIT_HOST;
-	default:
-		/*
-		 * There are only two USB controllers on Vybrid. Ideally we will
-		 * not reach here. However return USB_INIT_HOST if we do.
-		 */
-		return USB_INIT_HOST;
-	}
-}
-#endif
-
 /*
  * Backlight off before OS handover
  */
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index d4f5b18..b90077b 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -261,7 +261,7 @@
 	}
 
 	/* Cap product id to avoid issues with a yet unknown one */
-	if (tdx_hw_tag.prodid > (sizeof(toradex_modules) /
+	if (tdx_hw_tag.prodid >= (sizeof(toradex_modules) /
 				  sizeof(toradex_modules[0])))
 		tdx_hw_tag.prodid = 0;
 
@@ -418,6 +418,7 @@
 	int offset = 0;
 	int ret = CMD_RET_SUCCESS;
 	int err;
+	int force_overwrite = 0;
 
 	/* Allocate RAM area for config block */
 	config_block = memalign(ARCH_DMA_MINALIGN, size);
@@ -428,6 +429,11 @@
 
 	memset(config_block, 0xff, size);
 
+	if (argc >= 3) {
+		if (argv[2][0] == '-' && argv[2][1] == 'y')
+			force_overwrite = 1;
+	}
+
 	read_tdx_cfg_block();
 	if (valid_cfgblock) {
 #if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
@@ -448,24 +454,31 @@
 		       CONFIG_TDX_CFG_BLOCK_OFFSET);
 		goto out;
 #else
-		char message[CONFIG_SYS_CBSIZE];
-		sprintf(message,
-			"A valid Toradex config block is present, still recreate? [y/N] ");
+		if (!force_overwrite) {
+			char message[CONFIG_SYS_CBSIZE];
 
-		if (!cli_readline(message))
-			goto out;
+			sprintf(message,
+				"A valid Toradex config block is present, still recreate? [y/N] ");
 
-		if (console_buffer[0] != 'y' && console_buffer[0] != 'Y')
-			goto out;
+			if (!cli_readline(message))
+				goto out;
+
+			if (console_buffer[0] != 'y' &&
+			    console_buffer[0] != 'Y')
+				goto out;
+		}
 #endif
 	}
 
 	/* Parse new Toradex config block data... */
-	if (argc < 3)
+	if (argc < 3 || (force_overwrite && argc < 4)) {
 		err = get_cfgblock_interactive();
-	else
-		err = get_cfgblock_barcode(argv[2]);
-
+	} else {
+		if (force_overwrite)
+			err = get_cfgblock_barcode(argv[3]);
+		else
+			err = get_cfgblock_barcode(argv[2]);
+	}
 	if (err) {
 		ret = CMD_RET_FAILURE;
 		goto out;
@@ -549,8 +562,8 @@
 }
 
 U_BOOT_CMD(
-	cfgblock, 3, 0, do_cfgblock,
+	cfgblock, 4, 0, do_cfgblock,
 	"Toradex config block handling commands",
-	"create [barcode] - (Re-)create Toradex config block\n"
+	"create [-y] [barcode] - (Re-)create Toradex config block\n"
 	"cfgblock reload - Reload Toradex config block from flash"
 );
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index fde230c..2d560cc 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -12,6 +12,8 @@
 #include <asm/setup.h>
 #include "tdx-common.h"
 
+#define TORADEX_OUI 0x00142dUL
+
 #ifdef CONFIG_TDX_CFG_BLOCK
 static char tdx_serial_str[9];
 static char tdx_board_rev_str[6];
@@ -68,20 +70,25 @@
 	unsigned char ethaddr[6];
 
 	if (read_tdx_cfg_block()) {
-		printf("Missing Toradex config block\n");
+		printf("MISSING TORADEX CONFIG BLOCK\n");
+		tdx_eth_addr.oui = htonl(TORADEX_OUI << 8);
+		tdx_eth_addr.nic = htonl(tdx_serial << 8);
 		checkboard();
-		return 0;
+	} else {
+		sprintf(tdx_serial_str, "%08u", tdx_serial);
+		sprintf(tdx_board_rev_str, "V%1d.%1d%c",
+			tdx_hw_tag.ver_major,
+			tdx_hw_tag.ver_minor,
+			(char)tdx_hw_tag.ver_assembly + 'A');
+
+		env_set("serial#", tdx_serial_str);
+
+		printf("Model: Toradex %s %s, Serial# %s\n",
+		       toradex_modules[tdx_hw_tag.prodid],
+		       tdx_board_rev_str,
+		       tdx_serial_str);
 	}
 
-	/* board serial-number */
-	sprintf(tdx_serial_str, "%08u", tdx_serial);
-	sprintf(tdx_board_rev_str, "V%1d.%1d%c",
-		tdx_hw_tag.ver_major,
-		tdx_hw_tag.ver_minor,
-		(char)tdx_hw_tag.ver_assembly + 'A');
-
-	env_set("serial#", tdx_serial_str);
-
 	/*
 	 * Check if environment contains a valid MAC address,
 	 * set the one from config block if not
@@ -101,11 +108,6 @@
 	}
 #endif
 
-	printf("Model: Toradex %s %s, Serial# %s\n",
-	       toradex_modules[tdx_hw_tag.prodid],
-	       tdx_board_rev_str,
-	       tdx_serial_str);
-
 	return 0;
 }
 
diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS
index d7cbae8..00a31a93 100644
--- a/board/wandboard/MAINTAINERS
+++ b/board/wandboard/MAINTAINERS
@@ -1,6 +1,9 @@
 WANDBOARD BOARD
 M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
+F:	arch/arm/dts/imx6qdl-wandboard.dtsi
+F:	arch/arm/dts/imx6qdl-wandboard-revb1.dtsi
+F:	arch/arm/dts/imx6dl-wandboard-revb1.dts
 F:	board/wandboard/
 F:	include/configs/wandboard.h
 F:	configs/wandboard_defconfig
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 9c33500..000cb10 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -422,4 +422,96 @@
 	/* DDR initialization */
 	spl_dram_init();
 }
+
+#define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
+#define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* Carrier MicroSD Card Detect */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* SOM MicroSD Card Detect */
+	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	u32 index = 0;
+
+	/*
+	 * Following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    SOM MicroSD
+	 * mmc1                    Carrier board MicroSD
+	 */
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 4;
+			gpio_direction_input(USDHC3_CD_GPIO);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			gpio_direction_input(USDHC1_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+			       "(%d) then supported by the board (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 #endif
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 6af1b45..69fbc8b 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -22,8 +22,6 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <phy.h>
@@ -37,10 +35,6 @@
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
@@ -48,8 +42,6 @@
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
-#define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
-#define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
 #define ETH_PHY_RESET		IMX_GPIO_NR(3, 29)
 #define ETH_PHY_AR8035_POWER	IMX_GPIO_NR(7, 13)
 #define REV_DETECTION		IMX_GPIO_NR(2, 28)
@@ -68,28 +60,6 @@
 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	/* Carrier MicroSD Card Detect */
-	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	/* SOM MicroSD Card Detect */
-	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
 static iomux_v3_cfg_t const enet_pads[] = {
 	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
@@ -131,80 +101,20 @@
 	if (with_pmic) {
 		SETUP_IOMUX_PADS(enet_ar8035_power_pads);
 		/* enable AR8035 POWER */
+		gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
 		gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
 	}
 	/* wait until 3.3V of PHY and clock become stable */
 	mdelay(10);
 
 	/* Reset AR8031 PHY */
+	gpio_request(ETH_PHY_RESET, "PHY_RESET");
 	gpio_direction_output(ETH_PHY_RESET, 0);
 	mdelay(10);
 	gpio_set_value(ETH_PHY_RESET, 1);
 	udelay(100);
 }
 
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-	u32 index = 0;
-
-	/*
-	 * Following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    SOM MicroSD
-	 * mmc1                    Carrier board MicroSD
-	 */
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			SETUP_IOMUX_PADS(usdhc3_pads);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			usdhc_cfg[0].max_bus_width = 4;
-			gpio_direction_input(USDHC3_CD_GPIO);
-			break;
-		case 1:
-			SETUP_IOMUX_PADS(usdhc1_pads);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			usdhc_cfg[1].max_bus_width = 4;
-			gpio_direction_input(USDHC1_CD_GPIO);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-			       "(%d) then supported by the board (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
 	unsigned short val;
@@ -348,14 +258,29 @@
 
 static int detect_i2c(struct display_info_t const *dev)
 {
+#ifdef CONFIG_DM_I2C
+	struct udevice *bus, *udev;
+	int rc;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
+	if (rc)
+		return rc;
+	rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
+	if (rc)
+		return 0;
+	return 1;
+#else
 	return (0 == i2c_set_bus_num(dev->bus)) &&
 			(0 == i2c_probe(dev->addr));
+#endif
 }
 
 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 {
 	SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 
+	gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
+	gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
 	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 }
@@ -418,6 +343,7 @@
 
 	/* Disable LCD backlight */
 	SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
+	gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
 	gpio_direction_input(IMX_GPIO_NR(4, 20));
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
@@ -443,24 +369,30 @@
 
 int power_init_board(void)
 {
-	struct pmic *p;
-	u32 reg;
+	struct udevice *dev;
+	int reg, ret;
 
-	/* configure PFUZE100 PMIC */
-	power_pfuze100_init(PMIC_I2C_BUS);
-	p = pmic_get("PFUZE100");
-	if (p && !pmic_probe(p)) {
-		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
-		printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
-		with_pmic = true;
+	puts("PMIC:  ");
 
-		/* Set VGEN2 to 1.5V and enable */
-		pmic_reg_read(p, PFUZE100_VGEN2VOL, &reg);
-		reg &= ~(LDO_VOL_MASK);
-		reg |= (LDOA_1_50V | (1 << (LDO_EN)));
-		pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
+	ret = pmic_get("pfuze100", &dev);
+	if (ret < 0) {
+		printf("pmic_get() ret %d\n", ret);
+		return 0;
 	}
 
+	reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	if (reg < 0) {
+		printf("pmic_reg_read() ret %d\n", reg);
+		return 0;
+	}
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+	with_pmic = true;
+
+	/* Set VGEN2 to 1.5V and enable */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
+	reg &= ~(LDO_VOL_MASK);
+	reg |= (LDOA_1_50V | (1 << (LDO_EN)));
+	pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
 	return 0;
 }
 
@@ -531,13 +463,13 @@
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 #if defined(CONFIG_VIDEO_IPUV3)
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+	setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 	if (is_mx6dq() || is_mx6dqp()) {
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
-		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
+		setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info);
+		setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info);
 	} else {
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
-		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
+		setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+		setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
 	}
 
 	setup_display();
@@ -548,6 +480,8 @@
 
 int checkboard(void)
 {
+	gpio_request(REV_DETECTION, "REV_DETECT");
+
 	if (is_revd1())
 		puts("Board: Wandboard rev D1\n");
 	else if (is_revc1())
diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c
index 8b48ea3..27d44b7 100644
--- a/board/xilinx/zynq/cmds.c
+++ b/board/xilinx/zynq/cmds.c
@@ -414,9 +414,13 @@
 	u32 src_ptr;
 	char *endp;
 
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_FAILURE;
+
 	src_ptr = simple_strtoul(argv[2], &endp, 16);
 	if (*argv[2] == 0 || *endp != 0)
 		return CMD_RET_USAGE;
+
 	if (zynq_verify_image(src_ptr))
 		return CMD_RET_FAILURE;
 
@@ -432,6 +436,9 @@
 	u32 srcaddr, srclen, dstaddr, dstlen;
 	int status;
 
+	if (argc < 5 && argc > cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
 	srcaddr = simple_strtoul(argv[2], &endp, 16);
 	if (*argv[2] == 0 || *endp != 0)
 		return CMD_RET_USAGE;
@@ -485,7 +492,7 @@
 		return CMD_RET_USAGE;
 	zynq_cmd = find_cmd_tbl(argv[1], zynq_commands,
 				ARRAY_SIZE(zynq_commands));
-	if (!zynq_cmd || argc != zynq_cmd->maxargs)
+	if (!zynq_cmd)
 		return CMD_RET_USAGE;
 
 	ret = zynq_cmd->cmd(zynq_cmd, flag, argc, argv);
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index db27247..5189925b 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -170,6 +170,10 @@
 		.id = 0x62,
 		.name = "29dr",
 	},
+	{
+		.id = 0x66,
+		.name = "39dr",
+	},
 };
 #endif
 
@@ -482,18 +486,20 @@
 	{}
 };
 
-static u32 reset_reason(void)
+static int reset_reason(void)
 {
-	u32 ret;
-	int i;
+	u32 reg;
+	int i, ret;
 	const char *reason = NULL;
 
-	ret = readl(&crlapb_base->reset_reason);
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
+	if (ret)
+		return -EINVAL;
 
 	puts("Reset reason:\t");
 
 	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
-		if (ret & reset_reasons[i].bit) {
+		if (reg & reset_reasons[i].bit) {
 			reason = reset_reasons[i].name;
 			printf("%s ", reset_reasons[i].name);
 			break;
@@ -504,7 +510,9 @@
 
 	env_set("reset_reason", reason);
 
-	writel(~0, &crlapb_base->reset_reason);
+	ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
+	if (ret)
+		return -EINVAL;
 
 	return ret;
 }
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 3619a20..15ee4af 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -111,13 +111,13 @@
 	new_fdt_addr = (uintptr_t)map_sysmem(fdt_ram_start + 0x7f00000 +
 					     fdt_size, 0);
 	ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
-				 EFI_RUNTIME_SERVICES_DATA, fdt_pages,
+				 EFI_BOOT_SERVICES_DATA, fdt_pages,
 				 &new_fdt_addr);
 	if (ret != EFI_SUCCESS) {
 		/* If we can't put it there, put it somewhere */
 		new_fdt_addr = (ulong)memalign(EFI_PAGE_SIZE, fdt_size);
 		ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
-					 EFI_RUNTIME_SERVICES_DATA, fdt_pages,
+					 EFI_BOOT_SERVICES_DATA, fdt_pages,
 					 &new_fdt_addr);
 		if (ret != EFI_SUCCESS) {
 			printf("ERROR: Failed to reserve space for FDT\n");
diff --git a/cmd/dfu.c b/cmd/dfu.c
index c9ba062..91a750a 100644
--- a/cmd/dfu.c
+++ b/cmd/dfu.c
@@ -27,8 +27,10 @@
 #ifdef CONFIG_DFU_OVER_USB
 	char *usb_controller = argv[1];
 #endif
+#if defined(CONFIG_DFU_OVER_USB) || defined(CONFIG_DFU_OVER_TFTP)
 	char *interface = argv[2];
 	char *devstring = argv[3];
+#endif
 
 	int ret = 0;
 #ifdef CONFIG_DFU_OVER_TFTP
@@ -63,6 +65,7 @@
 
 U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
 	"Device Firmware Upgrade",
+	""
 #ifdef CONFIG_DFU_OVER_USB
 	"<USB_controller> <interface> <dev> [list]\n"
 	"  - device firmware upgrade via <USB_controller>\n"
diff --git a/cmd/fpga.c b/cmd/fpga.c
index 88a8e3f..b1f224b 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -343,9 +343,9 @@
 			return CMD_RET_FAILURE;
 		}
 
-		/* get fpga subimage data address and length */
-		if (fit_image_get_data(fit_hdr, noffset, &fit_data,
-				       &data_size)) {
+		/* get fpga subimage/external data address and length */
+		if (fit_image_get_data_and_size(fit_hdr, noffset,
+					       &fit_data, &data_size)) {
 			puts("Fpga subimage data not found\n");
 			return CMD_RET_FAILURE;
 		}
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index 753ae4f..570cf3a 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -14,6 +14,7 @@
 #include <part.h>
 #include <usb.h>
 #include <usb_mass_storage.h>
+#include <watchdog.h>
 
 static int ums_read_sector(struct ums *ums_dev,
 			   ulong start, lbaint_t blkcnt, void *buf)
@@ -226,6 +227,8 @@
 			rc = CMD_RET_SUCCESS;
 			goto cleanup_register;
 		}
+
+		WATCHDOG_RESET();
 	}
 
 cleanup_register:
diff --git a/common/board_r.c b/common/board_r.c
index 472987d..1ad44bb 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -154,6 +154,13 @@
 	gd->fdt_blob += gd->reloc_off;
 #endif
 #ifdef CONFIG_EFI_LOADER
+	/*
+	 * On the ARM architecture gd is mapped to a fixed register (r9 or x18).
+	 * As this register may be overwritten by an EFI payload we save it here
+	 * and restore it on every callback entered.
+	 */
+	efi_save_gd();
+
 	efi_runtime_relocate(gd->relocaddr, NULL);
 #endif
 
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 020f0d4..cc99c6b 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -145,6 +145,12 @@
 	data->usb_kbd_buffer[data->usb_in_pointer] = c;
 }
 
+static void usb_kbd_put_sequence(struct usb_kbd_pdata *data, char *s)
+{
+	for (; *s; s++)
+		usb_kbd_put_queue(data, *s);
+}
+
 /*
  * Set the LEDs. Since this is used in the irq routine, the control job is
  * issued with a timeout of 0. This means, that the job is queued without
@@ -235,9 +241,25 @@
 	}
 
 	/* Report keycode if any */
-	if (keycode) {
+	if (keycode)
 		debug("%c", keycode);
+
+	switch (keycode) {
+	case 0x0e:					/* Down arrow key */
+		usb_kbd_put_sequence(data, "\e[B");
+		break;
+	case 0x10:					/* Up arrow key */
+		usb_kbd_put_sequence(data, "\e[A");
+		break;
+	case 0x06:					/* Right arrow key */
+		usb_kbd_put_sequence(data, "\e[C");
+		break;
+	case 0x02:					/* Left arrow key */
+		usb_kbd_put_sequence(data, "\e[D");
+		break;
+	default:
 		usb_kbd_put_queue(data, keycode);
+		break;
 	}
 
 	return 0;
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 6afda72..ffe013f 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -56,7 +56,6 @@
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index a396a39..105ff01 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -64,7 +64,6 @@
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 1746df9..a37966b 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -60,7 +60,6 @@
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index d2d6f2f..ff131eb 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -62,7 +62,6 @@
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 86dabd3..0669520 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -9,12 +9,14 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_MISC_INIT_R=y
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -26,9 +28,7 @@
 CONFIG_SPL_USB_HOST_SUPPORT=y
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
@@ -38,30 +38,41 @@
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
 CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_SCSI=y
+CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
-CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
@@ -70,8 +81,8 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
 CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig
deleted file mode 100644
index b6ab528..0000000
--- a/configs/apalis_imx6_nospl_com_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_DFU_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4020
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig
deleted file mode 100644
index c972b11..0000000
--- a/configs/apalis_imx6_nospl_it_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_DFU_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4020
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index b852b4d..1dd2c3b 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -55,6 +55,7 @@
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index 7806d0a..e58541f 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -53,6 +53,7 @@
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index bad6aeb..0f2412b 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -53,6 +53,7 @@
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 0c8af40..8255d9f 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -35,7 +35,9 @@
 CONFIG_DM_GPIO=y
 CONFIG_HSDK_CREG_GPIO=y
 CONFIG_MMC=y
+CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 9e31b4a..439207f 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -2,15 +2,18 @@
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_VF610=y
 CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_TARGET_BK4R1=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_EEPROM=y
+# CONFIG_CMD_ELF is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -19,19 +22,44 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
+CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=NAND,nor0=NOR"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root);NOR:-(nor)"
+CONFIG_MTDIDS_DEFAULT="nand0=vf610_nfc,nor0=NOR"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=vf610_nfc:2048k(bootloader),128k(env1),128k(env2),10240k(initrd),40960k(dtbkernel),-(system);NOR:-(nor)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="bk4r1"
+CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1"
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_NETCONSOLE=y
 CONFIG_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_EEPROM_SIZE=32768
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
+CONFIG_NAND_VF610_NFC_DT=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
@@ -39,10 +67,18 @@
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_VYBRID=y
+CONFIG_DM_RTC=y
 CONFIG_RTC_M41T62=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 6b0d024..63cb240 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -84,7 +84,6 @@
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_FAT_WRITE=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index 4578f74..57cd54b 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -88,7 +88,6 @@
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_FAT_WRITE=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 739b078..31ba515 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -99,7 +99,6 @@
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_FAT_WRITE=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 2311c4f..d5d170f 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -74,5 +74,6 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index a6c36ed..944dd0d 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -50,6 +50,5 @@
 CONFIG_DM_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
 CONFIG_FAT_WRITE=y
 CONFIG_LZO=y
diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig
deleted file mode 100644
index fd8353e..0000000
--- a/configs/cl-som-am57x_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_CL_SOM_AM57X=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_FS_EXT4 is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_EEPROM_LAYOUT=y
-CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_SCSI_AHCI=y
-CONFIG_CMD_PCA953X=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=37
-CONFIG_LED_STATUS_STATE=2
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=48000000
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_MCS7830=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 6156ac2..4a46bb5 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -51,6 +51,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DWC_AHSATA=y
+# CONFIG_DWC_AHSATA_AHCI is not set
 CONFIG_DM_KEYBOARD=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -78,4 +79,5 @@
 CONFIG_USB_KEYBOARD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 2072281..bf05c68 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -9,12 +9,13 @@
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_MISC_INIT_R=y
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -26,9 +27,7 @@
 CONFIG_SPL_USB_HOST_SUPPORT=y
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri iMX6 # "
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
@@ -38,28 +37,38 @@
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
-CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
@@ -68,8 +77,7 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig
deleted file mode 100644
index 5e9490b..0000000
--- a/configs/colibri_imx6_nospl_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_COLIBRI_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Colibri iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DFU_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 4192501..8f6ccec 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -2,6 +2,7 @@
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_VF610=y
 CONFIG_SYS_TEXT_BASE=0x3f401000
+CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_TARGET_COLIBRI_VF=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_NR_DRAM_BANKS=1
@@ -16,11 +17,18 @@
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
 CONFIG_SYS_PROMPT="Colibri VFxx # "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADB is not set
@@ -45,17 +53,28 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
-CONFIG_DFU_MMC=y
 CONFIG_DFU_NAND=y
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
+CONFIG_DM_MMC=y
+# CONFIG_MMC_HW_PARTITIONING is not set
 CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
+CONFIG_NAND_VF610_NFC_DT=y
 CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_VYBRID=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y
@@ -72,4 +91,5 @@
 CONFIG_VIDEO=y
 CONFIG_SYS_CONSOLE_FG_COL=0x00
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_EFI_UNICODE_CAPITALIZATION is not set
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
index 6ca5d2b..c274c3a 100644
--- a/configs/dms-ba16-1g_defconfig
+++ b/configs/dms-ba16-1g_defconfig
@@ -53,5 +53,6 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
index 4ad3df6..6c27c38 100644
--- a/configs/dms-ba16_defconfig
+++ b/configs/dms-ba16_defconfig
@@ -52,5 +52,6 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 7319919..1db59c7 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -50,3 +50,17 @@
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_DM=y
+CONFIG_CMD_DM=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3"
+CONFIG_DM_MMC=y
+CONFIG_BLK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index 07171c7..2e04127 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -84,6 +84,7 @@
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_HEXDUMP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 0ed2209..275aa89 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -88,6 +88,7 @@
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_HEXDUMP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 57e4a99..477d205 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -87,6 +87,7 @@
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_HEXDUMP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index e0eb6bd..e28ceae 100644
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig
@@ -38,7 +38,9 @@
 CONFIG_DM_GPIO=y
 CONFIG_HSDK_CREG_GPIO=y
 CONFIG_MMC=y
+CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index 69c45b9..7b1f7ab 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -50,5 +50,5 @@
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index b53a501..1e26f7a 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -51,5 +51,5 @@
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 24e9971..223f732 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -67,5 +67,5 @@
 CONFIG_DEBUG_UART_MXC=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index cf149d6..8702426 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -50,5 +50,5 @@
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 5555e05..e830b2c 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -64,6 +64,7 @@
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_FAT_WRITE=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 320e14e..a2a0390 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -35,5 +35,6 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index e93e81f..dc0b3b3 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -31,5 +31,6 @@
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index 07f3a23..831d509 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -32,4 +32,5 @@
 CONFIG_PINCTRL_IMX5=y
 CONFIG_MXC_UART=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 4e16137..776fc8b 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -32,5 +32,6 @@
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 2854071..2a6183b 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -39,6 +39,16 @@
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_IMX_WATCHDOG=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM=y
+CONFIG_CMD_DM=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd"
+CONFIG_DM_MMC=y
+CONFIG_BLK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX5=y
+CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 506e3a7..f1c2fd4 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -39,5 +39,6 @@
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 3989352..8a5f9db 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -57,5 +57,6 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index d0f950b..23fd997 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -84,5 +84,6 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 0fd32aa..eaf0f01 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -95,5 +95,6 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index debe60b..5b3899d 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -59,5 +59,6 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 96d9c02..d89069a 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -59,5 +59,6 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 5bc4219..e9214d4 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -61,5 +61,6 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 37fa405..f1480f1 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -61,5 +61,6 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 1d3f015..b920db0 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -59,5 +59,6 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 5bf2b3a..c3b8032 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -59,5 +59,6 @@
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 4c9c1cb..103d918 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -58,6 +58,7 @@
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_FAT_WRITE=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index e207df5..fd093b3 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -9,7 +9,6 @@
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_EEPROM=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
@@ -18,23 +17,53 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nand0=NAND"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root)"
 CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="pcm052"
+CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_EEPROM_SIZE=32768
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
+CONFIG_NAND_VF610_NFC_DT=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_VYBRID=y
+CONFIG_DM_RTC=y
 CONFIG_RTC_M41T62=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index e3d16df..84561c8 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -35,5 +35,6 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig
index 51fa98d..db6ee8f 100644
--- a/configs/riotboard_spl_defconfig
+++ b/configs/riotboard_spl_defconfig
@@ -44,6 +44,7 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
 CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 995290c..4848013 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -6,7 +6,7 @@
 CONFIG_SPL=y
 CONFIG_IDENT_STRING="socfpga_stratix10"
 CONFIG_SPL_FS_FAT=y
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 6781adb..fd164fa 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -69,9 +69,9 @@
 CONFIG_STM32_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC2=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0483
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index a050cee..f82b770 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -60,9 +60,9 @@
 CONFIG_STM32_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC2=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0483
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 78beb9a..96b813d 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_TBS2910=y
 CONFIG_CMD_HDMIDETECT=y
+CONFIG_AHCI=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=3
 CONFIG_PRE_CONSOLE_BUFFER=y
@@ -14,6 +15,7 @@
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Matrix U-Boot> "
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FDT is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
@@ -28,7 +30,6 @@
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -36,15 +37,28 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_EFI_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1307=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
@@ -54,5 +68,7 @@
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_I2C_EDID=y
 CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+CONFIG_VIDEO_IPUV3=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index 08dfa24..e0e4dbd 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -33,6 +33,7 @@
 CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 5725487..ba0c844 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -10,6 +10,7 @@
 CONFIG_SPL=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_CMD_HDMIDETECT=y
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -32,15 +33,29 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revb1"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_SCSI=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
+CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index ba52187..ec92104 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -6,8 +6,10 @@
 CONFIG_SPL=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_ZYNQMP_NO_DDR=y
+# CONFIG_PSCI_RESET is not set
 # CONFIG_CMD_ZYNQMP is not set
 CONFIG_NR_DRAM_BANKS=1
+# CONFIG_EXPERT is not set
 # CONFIG_IMAGE_FORMAT_LEGACY is not set
 # CONFIG_BOARD_LATE_INIT is not set
 # CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig
index 6e07671..cd7d2f5 100644
--- a/configs/xilinx_zynqmp_zcu100_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig
@@ -85,8 +85,6 @@
 CONFIG_USB_ETH_CDC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_WDT=y
-CONFIG_WDT_CDNS=y
 CONFIG_SPL_GZIP=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/doc/README.uefi b/doc/README.uefi
index 66b6abe..1d1039a 100644
--- a/doc/README.uefi
+++ b/doc/README.uefi
@@ -14,9 +14,11 @@
 
 ## Development target
 
-The implementation of UEFI in U-Boot strives to reach the minimum requirements
-described in "Server Base Boot Requirements System Software on ARM Platforms -
-Version 1.1" [4].
+The implementation of UEFI in U-Boot strives to reach the requirements described
+in the "Embedded Base Boot Requirements (EBBR) Specification - Release v1.0"
+[4]. The "Server Base Boot Requirements System Software on ARM Platforms" [5]
+describes a superset of the EBBR specification and may be used as further
+reference.
 
 A full blown UEFI implementation would contradict the U-Boot design principle
 "keep it small".
@@ -344,5 +346,7 @@
   http://uefi.org/specifications - UEFI specifications
 * [2](./driver-model/README.txt) doc/driver-model/README.txt - Driver model
 * [3](./README.iscsi) doc/README.iscsi - iSCSI booting with U-Boot and iPXE
-* [4](https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11)
+* [4](https://github.com/ARM-software/ebbr/releases/download/v1.0/ebbr-v1.0.pdf)
+  Embedded Base Boot Requirements (EBBR) Specification - Release v1.0
+* [5](https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11)
   Server Base Boot Requirements System Software on ARM Platforms - Version 1.1
diff --git a/doc/device-tree-bindings/mmc/snps,dw-mmc.txt b/doc/device-tree-bindings/mmc/snps,dw-mmc.txt
new file mode 100644
index 0000000..69faefa
--- /dev/null
+++ b/doc/device-tree-bindings/mmc/snps,dw-mmc.txt
@@ -0,0 +1,33 @@
+Synopsys Designware Mobile Storage Host Controller extensions
+used in Synopsys ARC devboards
+
+Required Properties:
+
+* compatible: should be - "snps,dw-mshc".
+* bus-width: number of data lines connected to the controller.
+* clocks: from common clock binding: handle to biu and ciu clocks for the
+  bus interface unit clock and the card interface unit clock.
+* clock-names: from common clock binding: Shall be "biu" and "ciu".
+
+Optional properties:
+
+* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
+  specified, the default value of the fifo size is determined from the
+  controller registers.
+* fifo-mode: Don't use DMA.
+* max-frequency: Maximum operating clock frequency, driver uses 'ciu' clock
+  frequency if it is not set.
+
+Example:
+
+mmc0@f000a000 {
+	compatible = "snps,dw-mshc";
+	reg = <0xf000a000 0x400>;
+
+	bus-width = <4>;
+	fifo-depth = <256>;
+	clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+	clock-names = "biu", "ciu";
+	max-frequency = <25000000>;
+};
+
diff --git a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt
index 725ae71..da98407 100644
--- a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt
+++ b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt
@@ -23,6 +23,8 @@
 - compatible: must be "st,stm32mp1-usbphyc"
 - reg: address and length of the usb phy control register set
 - clocks: phandle + clock specifier for the PLL phy clock
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
 - #address-cells: number of address cells for phys sub-nodes, must be <1>
 - #size-cells: number of size cells for phys sub-nodes, must be <0>
 
@@ -40,8 +42,6 @@
 - reg: phy port index
 - phy-supply: phandle to the regulator providing 3V3 power to the PHY,
 	      see phy-bindings.txt in the same directory.
-- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
-- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
 - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
   port#1 and must be <1> for PHY port#2, to select USB controller
 
diff --git a/doc/device-tree-bindings/usb/dwc2.txt b/doc/device-tree-bindings/usb/dwc2.txt
new file mode 100644
index 0000000..61493f7
--- /dev/null
+++ b/doc/device-tree-bindings/usb/dwc2.txt
@@ -0,0 +1,58 @@
+Platform DesignWare HS OTG USB 2.0 controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : One of:
+  - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
+  - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
+  - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc;
+  - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
+  - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
+  - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
+  - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
+  - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs;
+  - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
+  - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
+  - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
+  - snps,dwc2: A generic DWC2 USB controller with default parameters.
+  - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs
+  configured in FS mode;
+  - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs
+  configured in HS mode;
+  - "st,stm32f7-hsotg": The DWC2 USB HS controller instance in STM32F7 SoCs
+    configured in HS mode;
+- reg : Should contain 1 register range (address and length)
+- interrupts : Should contain 1 interrupt
+- clocks: clock provider specifier
+- clock-names: shall be "otg"
+Refer to clk/clock-bindings.txt for generic clock consumer properties
+
+Optional properties:
+- phys: phy provider specifier
+- phy-names: shall be "usb2-phy"
+Refer to phy/phy-bindings.txt for generic phy consumer properties
+- dr_mode: shall be one of "host", "peripheral" and "otg"
+  Refer to usb/generic.txt
+- g-rx-fifo-size: size of rx fifo size in gadget mode.
+- g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode.
+- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode.
+- usb33d-supply: external VBUS and ID sensing comparators supply, in order to
+  perform OTG operation, used on STM32MP1 SoCs.
+- u-boot,force-b-session-valid: force B-peripheral session instead of relying on
+  VBUS sensing (only valid when dr_mode = "peripheral" and for u-boot).
+
+Deprecated properties:
+- g-use-dma: gadget DMA mode is automatically detected
+
+Example:
+
+        usb@101c0000 {
+                compatible = "ralink,rt3050-usb, snps,dwc2";
+                reg = <0x101c0000 40000>;
+                interrupts = <18>;
+		clocks = <&usb_otg_ahb_clk>;
+		clock-names = "otg";
+		phys = <&usbphy>;
+		phy-names = "usb2-phy";
+        };
diff --git a/doc/driver-model/MIGRATION.txt b/doc/driver-model/MIGRATION.txt
index 9575292..df659f3 100644
--- a/doc/driver-model/MIGRATION.txt
+++ b/doc/driver-model/MIGRATION.txt
@@ -77,7 +77,6 @@
 	drivers/spi/kirkwood_spi.c
 	drivers/spi/mxc_spi.c
 	drivers/spi/omap3_spi.c
-	drivers/spi/ti_qspi.c
 
 	Status: In progress
 	Deadline: 2019.07
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7ebee75..4e95a68 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -66,6 +66,14 @@
 	  Enable this driver to support the DWC AHSATA SATA controller found
 	  in i.MX5 and i.MX6 SoCs.
 
+config DWC_AHSATA_AHCI
+	bool "Enable DWC AHSATA AHCI driver support"
+	depends on DWC_AHSATA
+	depends on AHCI
+	default y
+	help
+	  Enable this option unless you need your private ahci implementation
+
 config FSL_SATA
 	bool "Enable Freescale SATA controller driver support"
 	select LIBATA
@@ -101,6 +109,14 @@
 	help
 	  Enable this driver to support the SIL3114 SATA controllers.
 
+config SUNXI_AHCI
+	bool "Enable Allwinner SATA driver support"
+	depends on AHCI
+	default y if ARCH_SUNXI
+	help
+	  Enable this driver to support the SATA controllers found in the
+	  Allwinner A10, A20 and R40 SoCs.
+
 config AHCI_MVEBU
 	bool "Marvell EBU AHCI SATA support"
 	depends on ARCH_MVEBU
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 10bed53..a69edb1 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -18,3 +18,4 @@
 obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_SANDBOX) += sata_sandbox.o
 obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
+obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
diff --git a/board/sunxi/ahci.c b/drivers/ata/ahci_sunxi.c
similarity index 93%
rename from board/sunxi/ahci.c
rename to drivers/ata/ahci_sunxi.c
index a79b80c..77b932a 100644
--- a/board/sunxi/ahci.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -70,15 +70,6 @@
 	return 0;
 }
 
-#ifndef CONFIG_DM_SCSI
-void scsi_init(void)
-{
-	if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0)
-		return;
-
-	ahci_init((void __iomem *)SUNXI_SATA_BASE);
-}
-#else
 static int sunxi_sata_probe(struct udevice *dev)
 {
 	ulong base;
@@ -121,6 +112,7 @@
 
 static const struct udevice_id sunxi_ahci_ids[] = {
 	{ .compatible = "allwinner,sun4i-a10-ahci" },
+	{ .compatible = "allwinner,sun8i-r40-ahci" },
 	{ }
 };
 
@@ -131,4 +123,3 @@
 	.bind		= sunxi_sata_bind,
 	.probe		= sunxi_sata_probe,
 };
-#endif
diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 4c5b984..afced8e 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -16,6 +16,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/sata.h>
 #include <linux/bitops.h>
 #include <linux/ctype.h>
 #include <linux/errno.h>
@@ -511,15 +512,9 @@
 static void dwc_ahsata_print_info(struct blk_desc *pdev)
 {
 	printf("SATA Device Info:\n\r");
-#ifdef CONFIG_SYS_64BIT_LBA
 	printf("S/N: %s\n\rProduct model number: %s\n\r"
-		"Firmware version: %s\n\rCapacity: %lld sectors\n\r",
+		"Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
 		pdev->product, pdev->vendor, pdev->revision, pdev->lba);
-#else
-	printf("S/N: %s\n\rProduct model number: %s\n\r"
-		"Firmware version: %s\n\rCapacity: %ld sectors\n\r",
-		pdev->product, pdev->vendor, pdev->revision, pdev->lba);
-#endif
 }
 
 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
@@ -754,7 +749,6 @@
 	u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
 	u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
 	u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
-	u64 n_sectors;
 	u8 port = uc_priv->hard_port_no;
 	ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
 
@@ -773,9 +767,8 @@
 	ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 	memcpy(pdev->vendor, product, sizeof(product));
 
-	/* Totoal sectors */
-	n_sectors = ata_id_n_sectors(id);
-	pdev->lba = (u32)n_sectors;
+	/* Total sectors */
+	pdev->lba = ata_id_n_sectors(id);
 
 	pdev->type = DEV_TYPE_HARDDISK;
 	pdev->blksz = ATA_SECT_SIZE;
@@ -1028,6 +1021,9 @@
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 	int ret;
 
+#if defined(CONFIG_MX6)
+	setup_sata();
+#endif
 	uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 			ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
 	uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
@@ -1075,4 +1071,24 @@
 	.ops		= &dwc_ahsata_blk_ops,
 };
 
+#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
+struct ahci_ops dwc_ahsata_ahci_ops = {
+	.port_status = dwc_ahsata_port_status,
+	.reset       = dwc_ahsata_bus_reset,
+	.scan        = dwc_ahsata_scan,
+};
+
+static const struct udevice_id dwc_ahsata_ahci_ids[] = {
+	{ .compatible = "fsl,imx6q-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(dwc_ahsata_ahci) = {
+	.name     = "dwc_ahsata_ahci",
+	.id       = UCLASS_AHCI,
+	.of_match = dwc_ahsata_ahci_ids,
+	.ops      = &dwc_ahsata_ahci_ops,
+	.probe    = dwc_ahsata_probe,
+};
+#endif
 #endif
diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index 482f093..b09c37d 100644
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -434,6 +434,8 @@
 	case lqspi_clk ... pcap_clk:
 	case sdio0_clk ... spi1_clk:
 		return zynq_clk_get_peripheral_rate(priv, id, 0);
+	case i2c0_aper_clk ... i2c1_aper_clk:
+		return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
 	default:
 		return -ENXIO;
 	}
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 30beac9..44abc4f 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -62,7 +62,6 @@
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
-	[RST_BUS_GMAC]		= RESET(0x2c0, BIT(17)),
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
 	[RST_BUS_SPI2]		= RESET(0x2c0, BIT(22)),
@@ -75,6 +74,8 @@
 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
 
+	[RST_BUS_GMAC]		= RESET(0x2c4, BIT(17)),
+
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 2b28a97..8f60b56 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,7 @@
 config ALTERA_SDRAM
 	bool "SoCFPGA DDR SDRAM driver"
 	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select RAM if TARGET_SOCFPGA_GEN5
+	select SPL_RAM if TARGET_SOCFPGA_GEN5
 	help
 	  Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 8210604..fcd89b6 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -3,14 +3,30 @@
  * Copyright Altera Corporation (C) 2014-2015
  */
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <div64.h>
+#include <ram.h>
+#include <reset.h>
 #include <watchdog.h>
 #include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
 #include <asm/arch/sdram.h>
 #include <asm/arch/system_manager.h>
 #include <asm/io.h>
 
+#include "sequencer.h"
+
+#ifdef CONFIG_SPL_BUILD
+
+struct altera_gen5_sdram_priv {
+	struct ram_info info;
+};
+
+struct altera_gen5_sdram_platdata {
+	struct socfpga_sdr *sdr;
+};
+
 struct sdram_prot_rule {
 	u32	sdram_start;	/* SDRAM start address */
 	u32	sdram_end;	/* SDRAM end address */
@@ -26,8 +42,8 @@
 
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_sdr_ctrl *sdr_ctrl =
-	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
+static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
 
 /**
  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
@@ -104,7 +120,8 @@
 }
 
 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
-static void sdram_set_rule(struct sdram_prot_rule *prule)
+static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
+			   struct sdram_prot_rule *prule)
 {
 	u32 lo_addr_bits;
 	u32 hi_addr_bits;
@@ -141,7 +158,8 @@
 	writel(0, &sdr_ctrl->prot_rule_rdwr);
 }
 
-static void sdram_get_rule(struct sdram_prot_rule *prule)
+static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
+			   struct sdram_prot_rule *prule)
 {
 	u32 addr;
 	u32 id;
@@ -172,7 +190,8 @@
 }
 
 static void
-sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
+sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl,
+			    const u32 sdram_start, const u32 sdram_end)
 {
 	struct sdram_prot_rule rule;
 	int rules;
@@ -185,7 +204,7 @@
 
 	for (rules = 0; rules < 20; rules++) {
 		rule.rule = rules;
-		sdram_set_rule(&rule);
+		sdram_set_rule(sdr_ctrl, &rule);
 	}
 
 	/* new rule: accept SDRAM */
@@ -200,13 +219,13 @@
 	rule.rule = 0;
 
 	/* set new rule */
-	sdram_set_rule(&rule);
+	sdram_set_rule(sdr_ctrl, &rule);
 
 	/* default rule: reject everything */
 	writel(0x3ff, &sdr_ctrl->protport_default);
 }
 
-static void sdram_dump_protection_config(void)
+static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl)
 {
 	struct sdram_prot_rule rule;
 	int rules;
@@ -216,7 +235,7 @@
 
 	for (rules = 0; rules < 20; rules++) {
 		rule.rule = rules;
-		sdram_get_rule(&rule);
+		sdram_get_rule(sdr_ctrl, &rule);
 		debug("Rule %d, rules ...\n", rules);
 		debug("    sdram start %x\n", rule.sdram_start);
 		debug("    sdram end   %x\n", rule.sdram_end);
@@ -322,7 +341,8 @@
  *
  * This function loads the register values into the SDRAM controller block.
  */
-static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
+static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
+			  const struct socfpga_sdram_config *cfg)
 {
 	const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 	const u32 dram_addrw = sdr_get_addr_rw(cfg);
@@ -426,7 +446,8 @@
  *
  * Initialize the SDRAM MMR.
  */
-int sdram_mmr_init_full(unsigned int sdr_phy_reg)
+int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
+			unsigned int sdr_phy_reg)
 {
 	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 	const unsigned int rows =
@@ -436,7 +457,7 @@
 
 	writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
 
-	sdr_load_regs(cfg);
+	sdr_load_regs(sdr_ctrl, cfg);
 
 	/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 	writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
@@ -459,9 +480,10 @@
 			SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 			1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 
-	sdram_set_protection_config(0, sdram_calculate_size() - 1);
+	sdram_set_protection_config(sdr_ctrl, 0,
+				    sdram_calculate_size(sdr_ctrl) - 1);
 
-	sdram_dump_protection_config();
+	sdram_dump_protection_config(sdr_ctrl);
 
 	return 0;
 }
@@ -472,7 +494,7 @@
  * Calculate SDRAM device size based on SDRAM controller parameters.
  * Size is specified in bytes.
  */
-unsigned long sdram_calculate_size(void)
+static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
 {
 	unsigned long temp;
 	unsigned long row, bank, col, cs, width;
@@ -534,3 +556,94 @@
 
 	return temp;
 }
+
+static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
+{
+	struct altera_gen5_sdram_platdata *plat = dev->platdata;
+
+	plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
+	if (!plat->sdr)
+		return -ENODEV;
+
+	return 0;
+}
+
+static int altera_gen5_sdram_probe(struct udevice *dev)
+{
+	int ret;
+	unsigned long sdram_size;
+	struct altera_gen5_sdram_platdata *plat = dev->platdata;
+	struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
+	struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
+	struct reset_ctl_bulk resets;
+
+	ret = reset_get_bulk(dev, &resets);
+	if (ret) {
+		dev_err(dev, "Can't get reset: %d\n", ret);
+		return -ENODEV;
+	}
+	reset_deassert_bulk(&resets);
+
+	if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
+		puts("SDRAM init failed.\n");
+		goto failed;
+	}
+
+	debug("SDRAM: Calibrating PHY\n");
+	/* SDRAM calibration */
+	if (sdram_calibration_full(plat->sdr) == 0) {
+		puts("SDRAM calibration failed.\n");
+		goto failed;
+	}
+
+	sdram_size = sdram_calculate_size(sdr_ctrl);
+	debug("SDRAM: %ld MiB\n", sdram_size >> 20);
+
+	/* Sanity check ensure correct SDRAM size specified */
+	if (get_ram_size(0, sdram_size) != sdram_size) {
+		puts("SDRAM size check failed!\n");
+		goto failed;
+	}
+
+	priv->info.base = 0;
+	priv->info.size = sdram_size;
+
+	return 0;
+
+failed:
+	reset_release_bulk(&resets);
+	return -ENODEV;
+}
+
+static int altera_gen5_sdram_get_info(struct udevice *dev,
+				      struct ram_info *info)
+{
+	struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
+
+	info->base = priv->info.base;
+	info->size = priv->info.size;
+
+	return 0;
+}
+
+static struct ram_ops altera_gen5_sdram_ops = {
+	.get_info = altera_gen5_sdram_get_info,
+};
+
+static const struct udevice_id altera_gen5_sdram_ids[] = {
+	{ .compatible = "altr,sdr-ctl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(altera_gen5_sdram) = {
+	.name = "altr_sdr_ctl",
+	.id = UCLASS_RAM,
+	.of_match = altera_gen5_sdram_ids,
+	.ops = &altera_gen5_sdram_ops,
+	.ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata),
+	.probe = altera_gen5_sdram_probe,
+	.priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv),
+};
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index a48567c..e4d4a02 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -7,12 +7,14 @@
 #include <common.h>
 #include <errno.h>
 #include <div64.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <wait_bit.h>
 #include <asm/arch/firewall_s10.h>
 #include <asm/arch/sdram_s10.h>
 #include <asm/arch/system_manager.h>
 #include <asm/arch/reset_manager.h>
+#include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -21,6 +23,8 @@
 
 #define DDR_CONFIG(A, B, C, R)	(((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
 
+#define PGTABLE_OFF	0x4000
+
 /* The followring are the supported configurations */
 u32 ddr_config[] = {
 	/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -134,6 +138,108 @@
 				 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 }
 
+static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
+{
+	phys_size_t i;
+
+	if (addr % CONFIG_SYS_CACHELINE_SIZE) {
+		printf("DDR: address 0x%llx is not cacheline size aligned.\n",
+		       addr);
+		hang();
+	}
+
+	if (size % CONFIG_SYS_CACHELINE_SIZE) {
+		printf("DDR: size 0x%llx is not multiple of cacheline size\n",
+		       size);
+		hang();
+	}
+
+	/* Use DC ZVA instruction to clear memory to zeros by a cache line */
+	for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
+		asm volatile("dc zva, %0"
+		     :
+		     : "r"(addr)
+		     : "memory");
+		addr += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+static void sdram_init_ecc_bits(bd_t *bd)
+{
+	phys_size_t size, size_init;
+	phys_addr_t start_addr;
+	int bank = 0;
+	unsigned int start = get_timer(0);
+
+	icache_enable();
+
+	start_addr = bd->bi_dram[0].start;
+	size = bd->bi_dram[0].size;
+
+	/* Initialize small block for page table */
+	memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
+	gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	start_addr += PGTABLE_SIZE + PGTABLE_OFF;
+	size -= (PGTABLE_OFF + PGTABLE_SIZE);
+	dcache_enable();
+
+	while (1) {
+		while (size) {
+			size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
+			sdram_clear_mem(start_addr, size_init);
+			size -= size_init;
+			start_addr += size_init;
+			WATCHDOG_RESET();
+		}
+
+		bank++;
+		if (bank >= CONFIG_NR_DRAM_BANKS)
+			break;
+
+		start_addr = bd->bi_dram[bank].start;
+		size = bd->bi_dram[bank].size;
+	}
+
+	dcache_disable();
+	icache_disable();
+
+	printf("SDRAM-ECC: Initialized success with %d ms\n",
+	       (unsigned int)get_timer(start));
+}
+
+static void sdram_size_check(bd_t *bd)
+{
+	phys_size_t total_ram_check = 0;
+	phys_size_t ram_check = 0;
+	phys_addr_t start = 0;
+	int bank;
+
+	/* Sanity check ensure correct SDRAM size specified */
+	debug("DDR: Running SDRAM size sanity check\n");
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start = bd->bi_dram[bank].start;
+		while (ram_check < bd->bi_dram[bank].size) {
+			ram_check += get_ram_size((void *)(start + ram_check),
+						 (phys_size_t)SZ_1G);
+		}
+		total_ram_check += ram_check;
+		ram_check = 0;
+	}
+
+	/* If the ram_size is 2GB smaller, we can assume the IO space is
+	 * not mapped in.  gd->ram_size is the actual size of the dram
+	 * not the accessible size.
+	 */
+	if (total_ram_check != gd->ram_size) {
+		puts("DDR: SDRAM size check failed!\n");
+		hang();
+	}
+
+	debug("DDR: SDRAM size check passed!\n");
+}
+
 /**
  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  *
@@ -144,6 +250,8 @@
 	u32 update_value, io48_value, ddrioctl;
 	u32 i;
 	int ret;
+	phys_size_t hw_size;
+	bd_t bd = {0};
 
 	/* Enable access to DDR from CPU master */
 	clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
@@ -335,9 +443,22 @@
 	unsigned long long size = sdram_calculate_size();
 	/* If the size is invalid, use default Config size */
 	if (size <= 0)
-		gd->ram_size = PHYS_SDRAM_1_SIZE;
+		hw_size = PHYS_SDRAM_1_SIZE;
 	else
-		gd->ram_size = size;
+		hw_size = size;
+
+	/* Get bank configuration from devicetree */
+	ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+				     (phys_size_t *)&gd->ram_size, &bd);
+	if (ret) {
+		puts("DDR: Failed to decode memory node\n");
+		return -1;
+	}
+
+	if (gd->ram_size != hw_size)
+		printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
+
+	printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 
 	/* Enable or disable the SDRAM ECC */
 	if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
@@ -351,6 +472,15 @@
 		setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
 			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+		writel(DDR_HMC_ERRINTEN_INTMASK,
+		       SOCFPGA_SDR_ADDRESS + ERRINTENS);
+
+		/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
+		writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
+
+		/* Initialize memory content if not from warm reset */
+		if (!cpu_has_been_warmreset())
+			sdram_init_ecc_bits(&bd);
 	} else {
 		clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
 			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
@@ -361,6 +491,8 @@
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 	}
 
+	sdram_size_check(&bd);
+
 	debug("DDR: HMC init success\n");
 	return 0;
 }
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 5e7a943..0e45262 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3705,12 +3705,19 @@
 	       &sdr_reg_file->trk_rfsh);
 }
 
-int sdram_calibration_full(void)
+int sdram_calibration_full(struct socfpga_sdr *sdr)
 {
 	struct param_type my_param;
 	struct gbl_type my_gbl;
 	u32 pass;
 
+	/*
+	 * For size reasons, this file uses hard coded addresses.
+	 * Check if we are called with the correct address.
+	 */
+	if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS)
+		return -ENODEV;
+
 	memset(&my_param, 0, sizeof(my_param));
 	memset(&my_gbl, 0, sizeof(my_gbl));
 
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index a5760b0..d7f6935 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -223,4 +223,39 @@
 	u32	mem_t_add;
 	u32	t_rl_add;
 };
+
+/* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */
+struct socfpga_sdr {
+	/* SDR_PHYGRP_SCCGRP_ADDRESS */
+	u8 _align1[0xe00];
+	/* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */
+	struct socfpga_sdr_scc_mgr sdr_scc_mgr;
+	u8 _align2[0x1bc];
+	/* SDR_PHYGRP_PHYMGRGRP_ADDRESS */
+	struct socfpga_phy_mgr_cmd phy_mgr_cmd;
+	u8 _align3[0x2c];
+	/* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */
+	struct socfpga_phy_mgr_cfg phy_mgr_cfg;
+	u8 _align4[0xfa0];
+	/* SDR_PHYGRP_RWMGRGRP_ADDRESS */
+	u8 rwmgr_grp[0x800];
+	/* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */
+	struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs;
+	u8 _align5[0x3f0];
+	/* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */
+	struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs;
+	u8 _align6[0x13f0];
+	/* SDR_PHYGRP_DATAMGRGRP_ADDRESS */
+	struct socfpga_data_mgr data_mgr;
+	u8 _align7[0x7f0];
+	/* SDR_PHYGRP_REGFILEGRP_ADDRESS */
+	struct socfpga_sdr_reg_file sdr_reg_file;
+	u8 _align8[0x7c8];
+	/* SDR_CTRLGRP_ADDRESS */
+	struct socfpga_sdr_ctrl sdr_ctrl;
+	u8 _align9[0xea4];
+};
+
+int sdram_calibration_full(struct socfpga_sdr *sdr);
+
 #endif /* _SEQUENCER_H_ */
diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index 4d264c9..4268628 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -17,6 +17,7 @@
 static void getvar_serialno(char *var_parameter, char *response);
 static void getvar_version_baseband(char *var_parameter, char *response);
 static void getvar_product(char *var_parameter, char *response);
+static void getvar_platform(char *var_parameter, char *response);
 static void getvar_current_slot(char *var_parameter, char *response);
 static void getvar_slot_suffixes(char *var_parameter, char *response);
 static void getvar_has_slot(char *var_parameter, char *response);
@@ -56,13 +57,16 @@
 		.variable = "product",
 		.dispatch = getvar_product
 	}, {
+		.variable = "platform",
+		.dispatch = getvar_platform
+	}, {
 		.variable = "current-slot",
 		.dispatch = getvar_current_slot
 	}, {
 		.variable = "slot-suffixes",
 		.dispatch = getvar_slot_suffixes
 	}, {
-		.variable = "has_slot",
+		.variable = "has-slot",
 		.dispatch = getvar_has_slot
 #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
 	}, {
@@ -117,6 +121,16 @@
 		fastboot_fail("Board not set", response);
 }
 
+static void getvar_platform(char *var_parameter, char *response)
+{
+	const char *p = env_get("platform");
+
+	if (p)
+		fastboot_okay(p, response);
+	else
+		fastboot_fail("platform not set", response);
+}
+
 static void getvar_current_slot(char *var_parameter, char *response)
 {
 	/* A/B not implemented, for now always return _a */
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index 4c1c7fd..90ca81d 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -31,13 +31,13 @@
 
 	ret = part_get_info_by_name(dev_desc, name, info);
 	if (ret < 0) {
-		/* strlen("fastboot_partition_alias_") + 32(part_name) + 1 */
-		char env_alias_name[25 + 32 + 1];
+		/* strlen("fastboot_partition_alias_") + PART_NAME_LEN + 1 */
+		char env_alias_name[25 + PART_NAME_LEN + 1];
 		char *aliased_part_name;
 
 		/* check for alias */
 		strcpy(env_alias_name, "fastboot_partition_alias_");
-		strncat(env_alias_name, name, 32);
+		strncat(env_alias_name, name, PART_NAME_LEN);
 		aliased_part_name = env_get(env_alias_name);
 		if (aliased_part_name != NULL)
 			ret = part_get_info_by_name(dev_desc,
@@ -308,8 +308,8 @@
 		fastboot_fail("block device not found", response);
 		return -ENOENT;
 	}
-	if (!part_name) {
-		fastboot_fail("partition not found", response);
+	if (!part_name || !strcmp(part_name, "")) {
+		fastboot_fail("partition not given", response);
 		return -ENOENT;
 	}
 
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 499310d..069c63b 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -408,6 +408,8 @@
 	if (bstype != BIT_PARTIAL)
 		zynq_slcr_devcfg_enable();
 
+	puts("INFO:post config was not run, please run manually if needed\n");
+
 	return FPGA_SUCCESS;
 }
 
@@ -421,7 +423,8 @@
 	loff_t blocksize, actread;
 	loff_t pos = 0;
 	int fstype;
-	char *interface, *dev_part, *filename;
+	char *interface, *dev_part;
+	const char *filename;
 
 	blocksize = fsinfo->blocksize;
 	interface = fsinfo->interface;
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index d6e677f..0e645f5 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -128,6 +128,8 @@
 
 config MXC_OCOTP
 	bool "Enable MXC OCOTP Driver"
+	depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610
+	default y
 	help
 	  If you say Y here, you will get support for the One Time
 	  Programmable memory pages that are stored on the some
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 04a4e77..c34dd5d 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -222,6 +222,16 @@
 	  Synopsys DesignWare Memory Card Interface driver. Select this option
 	  for platforms based on Altera SOCFPGA.
 
+config MMC_DW_SNPS
+	bool "Extensions for DW Memory Card Interface used in Synopsys ARC devboards"
+	depends on MMC_DW
+	depends on DM_MMC
+	depends on OF_CONTROL
+	depends on CLK
+	help
+	  This selects support for Synopsys DesignWare Memory Card Interface driver
+	  extensions used in various Synopsys ARC devboards.
+
 config MMC_MESON_GX
 	bool "Meson GX EMMC controller support"
 	depends on DM_MMC && BLK && ARCH_MESON
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 7892c46..0076fc3 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -24,6 +24,7 @@
 obj-$(CONFIG_MMC_DW_K3)			+= hi6220_dw_mmc.o
 obj-$(CONFIG_MMC_DW_ROCKCHIP)		+= rockchip_dw_mmc.o
 obj-$(CONFIG_MMC_DW_SOCFPGA)		+= socfpga_dw_mmc.o
+obj-$(CONFIG_MMC_DW_SNPS)		+= snps_dw_mmc.o
 obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
 obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c
new file mode 100644
index 0000000..5a413f0
--- /dev/null
+++ b/drivers/mmc/snps_dw_mmc.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ * extensions used in various Synopsys ARC devboards.
+ *
+ * Copyright (C) 2019 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dwmmc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/libfdt.h>
+#include <linux/err.h>
+#include <malloc.h>
+
+#define CLOCK_MIN		400000	/*  400 kHz */
+#define FIFO_MIN		8
+#define FIFO_MAX		4096
+
+struct snps_dwmci_plat {
+	struct mmc_config	cfg;
+	struct mmc		mmc;
+};
+
+struct snps_dwmci_priv_data {
+	struct dwmci_host	host;
+	u32			f_max;
+};
+
+static int snps_dwmmc_clk_setup(struct udevice *dev)
+{
+	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
+	struct dwmci_host *host = &priv->host;
+
+	struct clk clk_ciu, clk_biu;
+	int ret;
+
+	ret = clk_get_by_name(dev, "ciu", &clk_ciu);
+	if (ret)
+		goto clk_err;
+
+	ret = clk_enable(&clk_ciu);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+		goto clk_err_ciu;
+
+	host->bus_hz = clk_get_rate(&clk_ciu);
+	if (host->bus_hz < CLOCK_MIN) {
+		ret = -EINVAL;
+		goto clk_err_ciu_dis;
+	}
+
+	ret = clk_get_by_name(dev, "biu", &clk_biu);
+	if (ret)
+		goto clk_err_ciu_dis;
+
+	ret = clk_enable(&clk_biu);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+		goto clk_err_biu;
+
+	return 0;
+
+clk_err_biu:
+	clk_free(&clk_biu);
+clk_err_ciu_dis:
+	clk_disable(&clk_ciu);
+clk_err_ciu:
+	clk_free(&clk_ciu);
+clk_err:
+	dev_err(dev, "failed to setup clocks, ret %d\n", ret);
+
+	return ret;
+}
+
+static int snps_dwmmc_ofdata_to_platdata(struct udevice *dev)
+{
+	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
+	struct dwmci_host *host = &priv->host;
+	u32 fifo_depth;
+	int ret;
+
+	host->ioaddr = devfdt_get_addr_ptr(dev);
+
+	/*
+	 * If fifo-depth is unset don't set fifoth_val - we will try to
+	 * auto detect it.
+	 */
+	ret = dev_read_u32(dev, "fifo-depth", &fifo_depth);
+	if (!ret) {
+		if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX)
+			return -EINVAL;
+
+		host->fifoth_val = MSIZE(0x2) |
+				   RX_WMARK(fifo_depth / 2 - 1) |
+				   TX_WMARK(fifo_depth / 2);
+	}
+
+	host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
+	if (host->buswidth != 1 && host->buswidth != 4 && host->buswidth != 8)
+		return -EINVAL;
+
+	/*
+	 * If max-frequency is unset don't set priv->f_max - we will use
+	 * host->bus_hz in probe() instead.
+	 */
+	ret = dev_read_u32(dev, "max-frequency", &priv->f_max);
+	if (!ret && priv->f_max < CLOCK_MIN)
+		return -EINVAL;
+
+	host->fifo_mode = dev_read_bool(dev, "fifo-mode");
+	host->name = dev->name;
+	host->dev_index = 0;
+	host->priv = priv;
+
+	return 0;
+}
+
+int snps_dwmmc_getcd(struct udevice *dev)
+{
+	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
+	struct dwmci_host *host = &priv->host;
+
+	return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
+}
+
+struct dm_mmc_ops snps_dwmci_dm_ops;
+
+static int snps_dwmmc_probe(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+	struct snps_dwmci_plat *plat = dev_get_platdata(dev);
+#endif
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
+	struct dwmci_host *host = &priv->host;
+	unsigned int clock_max;
+	int ret;
+
+	/* Extend generic 'dm_dwmci_ops' with our 'getcd' implementation */
+	memcpy(&snps_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops));
+	snps_dwmci_dm_ops.get_cd = snps_dwmmc_getcd;
+
+	ret = snps_dwmmc_clk_setup(dev);
+	if (ret)
+		return ret;
+
+	if (!priv->f_max)
+		clock_max = host->bus_hz;
+	else
+		clock_max = min_t(unsigned int, host->bus_hz, priv->f_max);
+
+#ifdef CONFIG_BLK
+	dwmci_setup_cfg(&plat->cfg, host, clock_max, CLOCK_MIN);
+	host->mmc = &plat->mmc;
+#else
+	ret = add_dwmci(host, clock_max, CLOCK_MIN);
+	if (ret)
+		return ret;
+#endif
+	host->mmc->priv = &priv->host;
+	upriv->mmc = host->mmc;
+	host->mmc->dev = dev;
+
+	return dwmci_probe(dev);
+}
+
+static int snps_dwmmc_bind(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+	struct snps_dwmci_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id snps_dwmmc_ids[] = {
+	{ .compatible = "snps,dw-mshc" },
+	{ }
+};
+
+U_BOOT_DRIVER(snps_dwmmc_drv) = {
+	.name				= "snps_dw_mmc",
+	.id				= UCLASS_MMC,
+	.of_match			= snps_dwmmc_ids,
+	.ofdata_to_platdata		= snps_dwmmc_ofdata_to_platdata,
+	.ops				= &snps_dwmci_dm_ops,
+	.bind				= snps_dwmmc_bind,
+	.probe				= snps_dwmmc_probe,
+	.priv_auto_alloc_size		= sizeof(struct snps_dwmci_priv_data),
+	.platdata_auto_alloc_size	= sizeof(struct snps_dwmci_plat),
+};
diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h
index 019deda..63ae828 100644
--- a/drivers/mtd/nand/raw/denali.h
+++ b/drivers/mtd/nand/raw/denali.h
@@ -10,6 +10,7 @@
 #include <linux/bitops.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/types.h>
+#include <reset.h>
 
 #define DEVICE_RESET				0x0
 #define     DEVICE_RESET__BANK(bank)			BIT(bank)
@@ -315,6 +316,7 @@
 	void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
 	void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
 			  int page, int write);
+	struct reset_ctl_bulk resets;
 };
 
 #define DENALI_CAP_HW_ECC_FIXUP			BIT(0)
diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c
index d384b97..0ce8132 100644
--- a/drivers/mtd/nand/raw/denali_dt.c
+++ b/drivers/mtd/nand/raw/denali_dt.c
@@ -131,15 +131,30 @@
 		denali->clk_x_rate = 200000000;
 	}
 
+	ret = reset_get_bulk(dev, &denali->resets);
+	if (ret)
+		dev_warn(dev, "Can't get reset: %d\n", ret);
+	else
+		reset_deassert_bulk(&denali->resets);
+
 	return denali_init(denali);
 }
 
+static int denali_dt_remove(struct udevice *dev)
+{
+	struct denali_nand_info *denali = dev_get_priv(dev);
+
+	return reset_release_bulk(&denali->resets);
+}
+
 U_BOOT_DRIVER(denali_nand_dt) = {
 	.name = "denali-nand-dt",
 	.id = UCLASS_MISC,
 	.of_match = denali_nand_dt_ids,
 	.probe = denali_dt_probe,
 	.priv_auto_alloc_size = sizeof(struct denali_nand_info),
+	.remove = denali_dt_remove,
+	.flags = DM_FLAG_OS_PREPARE,
 };
 
 void board_nand_init(void)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 77d0b3a..d0e5426 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -190,7 +190,7 @@
 
 config FEC_MXC
 	bool "FEC Ethernet controller"
-	depends on MX5 || MX6 || MX7 || IMX8
+	depends on MX5 || MX6 || MX7 || IMX8 || VF610
 	help
 	  This driver supports the 10/100 Fast Ethernet controller for
 	  NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 84f010d..a672250 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1491,6 +1491,7 @@
 	{ .compatible = "fsl,imx6ul-fec" },
 	{ .compatible = "fsl,imx53-fec" },
 	{ .compatible = "fsl,imx7d-fec" },
+	{ .compatible = "fsl,mvf600-fec" },
 	{ }
 };
 
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index c979844..98bd7a5 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -14,12 +14,14 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <fdt_support.h>
 #include <linux/err.h>
 #include <malloc.h>
 #include <miiphy.h>
 #include <net.h>
+#include <reset.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 #ifdef CONFIG_DM_GPIO
 #include <asm-generic/gpio.h>
@@ -135,6 +137,8 @@
 	phys_addr_t sysctl_reg;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
+	struct clk tx_clk;
+	struct reset_ctl tx_rst;
 #ifdef CONFIG_DM_GPIO
 	struct gpio_desc reset_gpio;
 #endif
@@ -285,10 +289,18 @@
 	int ret;
 	u32 reg;
 
-	reg = readl(priv->sysctl_reg + 0x30);
+	if (priv->variant == R40_GMAC) {
+		/* Select RGMII for R40 */
+		reg = readl(priv->sysctl_reg + 0x164);
+		reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+		       CCM_GMAC_CTRL_GPIT_RGMII |
+		       CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
 
-	if (priv->variant == R40_GMAC)
+		writel(reg, priv->sysctl_reg + 0x164);
 		return 0;
+	}
+
+	reg = readl(priv->sysctl_reg + 0x30);
 
 	if (priv->variant == H3_EMAC) {
 		ret = sun8i_emac_set_syscon_ephy(priv, &reg);
@@ -639,9 +651,24 @@
 	return _sun8i_write_hwaddr(priv, pdata->enetaddr);
 }
 
-static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
+static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
 {
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int ret;
+
+	ret = clk_enable(&priv->tx_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable TX clock\n");
+		return ret;
+	}
+
+	if (reset_valid(&priv->tx_rst)) {
+		ret = reset_deassert(&priv->tx_rst);
+		if (ret) {
+			dev_err(dev, "failed to deassert TX reset\n");
+			goto err_tx_clk;
+		}
+	}
 
 	if (priv->variant == H3_EMAC) {
 		/* Only H3/H5 have clock controls for internal EPHY */
@@ -656,26 +683,11 @@
 		}
 	}
 
-	if (priv->variant == R40_GMAC) {
-		/* Set clock gating for emac */
-		setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
+	return 0;
 
-		/* De-assert EMAC */
-		setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
-
-		/* Select RGMII for R40 */
-		setbits_le32(&ccm->gmac_clk_cfg,
-			     CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
-			     CCM_GMAC_CTRL_GPIT_RGMII);
-		setbits_le32(&ccm->gmac_clk_cfg,
-			     CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
-	} else {
-		/* Set clock gating for emac */
-		setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
-
-		/* De-assert EMAC */
-		setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
-	}
+err_tx_clk:
+	clk_disable(&priv->tx_clk);
+	return ret;
 }
 
 #if defined(CONFIG_DM_GPIO)
@@ -802,10 +814,14 @@
 	struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
 	struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
 	struct emac_eth_dev *priv = dev_get_priv(dev);
+	int ret;
 
 	priv->mac_reg = (void *)pdata->iobase;
 
-	sun8i_emac_board_setup(priv);
+	ret = sun8i_emac_board_setup(priv);
+	if (ret)
+		return ret;
+
 	sun8i_emac_set_syscon(sun8i_pdata, priv);
 
 	sun8i_mdio_init(dev->name, dev);
@@ -834,8 +850,8 @@
 	int offset = 0;
 #ifdef CONFIG_DM_GPIO
 	int reset_flags = GPIOD_IS_OUT;
-	int ret = 0;
 #endif
+	int ret;
 
 	pdata->iobase = devfdt_get_addr(dev);
 	if (pdata->iobase == FDT_ADDR_T_NONE) {
@@ -850,25 +866,35 @@
 		return -EINVAL;
 	}
 
-	if (priv->variant != R40_GMAC) {
-		offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
-		if (offset < 0) {
-			debug("%s: cannot find syscon node\n", __func__);
-			return -EINVAL;
-		}
-		reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
-		if (!reg) {
-			debug("%s: cannot find reg property in syscon node\n",
-			      __func__);
-			return -EINVAL;
-		}
-		priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
-							 offset, reg);
-		if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
-			debug("%s: Cannot find syscon base address\n",
-			      __func__);
-			return -EINVAL;
-		}
+	ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
+	if (ret) {
+		dev_err(dev, "failed to get TX clock\n");
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
+	if (ret && ret != -ENOENT) {
+		dev_err(dev, "failed to get TX reset\n");
+		return ret;
+	}
+
+	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+	if (offset < 0) {
+		debug("%s: cannot find syscon node\n", __func__);
+		return -EINVAL;
+	}
+
+	reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+	if (!reg) {
+		debug("%s: cannot find reg property in syscon node\n",
+		      __func__);
+		return -EINVAL;
+	}
+	priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+						 offset, reg);
+	if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+		debug("%s: Cannot find syscon base address\n", __func__);
+		return -EINVAL;
 	}
 
 	pdata->phy_interface = -1;
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 8dbd3c5..9a5f7fd 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <linux/err.h>
 #include <malloc.h>
@@ -157,6 +158,7 @@
 
 struct emac_eth_dev {
 	struct emac_regs *regs;
+	struct clk clk;
 	struct mii_dev *bus;
 	struct phy_device *phydev;
 	int link_printed;
@@ -500,14 +502,12 @@
 	return 0;
 }
 
-static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
 {
-	struct sunxi_ccm_reg *const ccm =
-		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_sramc_regs *sram =
 		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
 	struct emac_regs *regs = priv->regs;
-	int pin;
+	int pin, ret;
 
 	/* Map SRAM to EMAC */
 	setbits_le32(&sram->ctrl1, 0x5 << 2);
@@ -517,10 +517,16 @@
 		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
 
 	/* Set up clock gating */
-	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+	ret = clk_enable(&priv->clk);
+	if (ret) {
+		dev_err(dev, "failed to enable emac clock\n");
+		return ret;
+	}
 
 	/* Set MII clock */
 	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
+
+	return 0;
 }
 
 static int sunxi_emac_eth_start(struct udevice *dev)
@@ -557,9 +563,19 @@
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct emac_eth_dev *priv = dev_get_priv(dev);
+	int ret;
 
 	priv->regs = (struct emac_regs *)pdata->iobase;
-	sunxi_emac_board_setup(priv);
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret) {
+		dev_err(dev, "failed to get emac clock\n");
+		return ret;
+	}
+
+	ret = sunxi_emac_board_setup(priv);
+	if (ret)
+		return ret;
 
 	return sunxi_emac_init_phy(priv, dev);
 }
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3bd0093..033efb8 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -261,45 +261,6 @@
 			    ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 }
 
-static int phy_detection(struct udevice *dev)
-{
-	int i;
-	u16 phyreg = 0;
-	struct zynq_gem_priv *priv = dev->priv;
-
-	if (priv->phyaddr != -1) {
-		phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
-		if ((phyreg != 0xFFFF) &&
-		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
-			/* Found a valid PHY address */
-			debug("Default phy address %d is valid\n",
-			      priv->phyaddr);
-			return 0;
-		} else {
-			debug("PHY address is not setup correctly %d\n",
-			      priv->phyaddr);
-			priv->phyaddr = -1;
-		}
-	}
-
-	debug("detecting phy address\n");
-	if (priv->phyaddr == -1) {
-		/* detect the PHY address */
-		for (i = 31; i >= 0; i--) {
-			phyread(priv, i, PHY_DETECT_REG, &phyreg);
-			if ((phyreg != 0xFFFF) &&
-			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
-				/* Found a valid PHY address */
-				priv->phyaddr = i;
-				debug("Found valid phy address, %d\n", i);
-				return 0;
-			}
-		}
-	}
-	printf("PHY is not detected\n");
-	return -1;
-}
-
 static int zynq_gem_setup_mac(struct udevice *dev)
 {
 	u32 i, macaddrlow, macaddrhigh;
@@ -345,28 +306,20 @@
 	/* Enable only MDIO bus */
 	writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 
-	if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
-	    (priv->interface != PHY_INTERFACE_MODE_GMII)) {
-		ret = phy_detection(dev);
-		if (ret) {
-			printf("GEM PHY init failed\n");
-			return ret;
-		}
-	}
-
 	priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 				   priv->interface);
 	if (!priv->phydev)
 		return -ENODEV;
 
-	priv->phydev->supported &= supported | ADVERTISED_Pause |
-				  ADVERTISED_Asym_Pause;
 	if (priv->max_speed) {
 		ret = phy_set_supported(priv->phydev, priv->max_speed);
 		if (ret)
 			return ret;
 	}
 
+	priv->phydev->supported &= supported | ADVERTISED_Pause |
+				  ADVERTISED_Asym_Pause;
+
 	priv->phydev->advertising = priv->phydev->supported;
 	priv->phydev->node = priv->phy_of_node;
 
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index 8e98b4b..6f11190 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -37,7 +37,8 @@
 
 #define MAX_PHYS		2
 
-#define PLL_LOCK_TIME_US	100
+/* max 100 us for PLL lock and 100 us for PHY init */
+#define PLL_INIT_TIME_US	200
 #define PLL_PWR_DOWN_TIME_US	5
 #define PLL_FVCO		2880	 /* in MHz */
 #define PLL_INFF_MIN_RATE	19200000 /* in Hz */
@@ -51,17 +52,17 @@
 struct stm32_usbphyc {
 	fdt_addr_t base;
 	struct clk clk;
+	struct udevice *vdda1v1;
+	struct udevice *vdda1v8;
 	struct stm32_usbphyc_phy {
 		struct udevice *vdd;
-		struct udevice *vdda1v1;
-		struct udevice *vdda1v8;
-		int index;
 		bool init;
 		bool powered;
 	} phys[MAX_PHYS];
 };
 
-void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
+static void stm32_usbphyc_get_pll_params(u32 clk_rate,
+					 struct pll_params *pll_params)
 {
 	unsigned long long fvco, ndiv, frac;
 
@@ -154,6 +155,18 @@
 	if (pllen && stm32_usbphyc_is_init(usbphyc))
 		goto initialized;
 
+	if (usbphyc->vdda1v1) {
+		ret = regulator_set_enable(usbphyc->vdda1v1, true);
+		if (ret)
+			return ret;
+	}
+
+	if (usbphyc->vdda1v8) {
+		ret = regulator_set_enable(usbphyc->vdda1v8, true);
+		if (ret)
+			return ret;
+	}
+
 	if (pllen) {
 		clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 		udelay(PLL_PWR_DOWN_TIME_US);
@@ -165,11 +178,8 @@
 
 	setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 
-	/*
-	 * We must wait PLL_LOCK_TIME_US before checking that PLLEN
-	 * bit is still set
-	 */
-	udelay(PLL_LOCK_TIME_US);
+	/* We must wait PLL_INIT_TIME_US before using PHY */
+	udelay(PLL_INIT_TIME_US);
 
 	if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
 		return -EIO;
@@ -184,6 +194,7 @@
 {
 	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+	int ret;
 
 	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 	usbphyc_phy->init = false;
@@ -203,6 +214,18 @@
 	if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
 		return -EIO;
 
+	if (usbphyc->vdda1v1) {
+		ret = regulator_set_enable(usbphyc->vdda1v1, false);
+		if (ret)
+			return ret;
+	}
+
+	if (usbphyc->vdda1v8) {
+		ret = regulator_set_enable(usbphyc->vdda1v8, false);
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
@@ -213,17 +236,6 @@
 	int ret;
 
 	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
-	if (usbphyc_phy->vdda1v1) {
-		ret = regulator_set_enable(usbphyc_phy->vdda1v1, true);
-		if (ret)
-			return ret;
-	}
-
-	if (usbphyc_phy->vdda1v8) {
-		ret = regulator_set_enable(usbphyc_phy->vdda1v8, true);
-		if (ret)
-			return ret;
-	}
 	if (usbphyc_phy->vdd) {
 		ret = regulator_set_enable(usbphyc_phy->vdd, true);
 		if (ret)
@@ -247,18 +259,6 @@
 	if (stm32_usbphyc_is_powered(usbphyc))
 		return 0;
 
-	if (usbphyc_phy->vdda1v1) {
-		ret = regulator_set_enable(usbphyc_phy->vdda1v1, false);
-		if (ret)
-			return ret;
-	}
-
-	if (usbphyc_phy->vdda1v8) {
-		ret = regulator_set_enable(usbphyc_phy->vdda1v8, false);
-		if (ret)
-			return ret;
-	}
-
 	if (usbphyc_phy->vdd) {
 		ret = regulator_set_enable(usbphyc_phy->vdd, false);
 		if (ret)
@@ -298,19 +298,20 @@
 static int stm32_usbphyc_of_xlate(struct phy *phy,
 				  struct ofnode_phandle_args *args)
 {
-	if (args->args_count > 1) {
-		pr_debug("%s: invalid args_count: %d\n", __func__,
-			 args->args_count);
-		return -EINVAL;
-	}
+	if (args->args_count < 1)
+		return -ENODEV;
 
 	if (args->args[0] >= MAX_PHYS)
 		return -ENODEV;
 
-	if (args->args_count)
-		phy->id = args->args[0];
-	else
-		phy->id = 0;
+	phy->id = args->args[0];
+
+	if ((phy->id == 0 && args->args_count != 1) ||
+	    (phy->id == 1 && args->args_count != 2)) {
+		dev_err(dev, "invalid number of cells for phy port%ld\n",
+			phy->id);
+		return -EINVAL;
+	}
 
 	return 0;
 }
@@ -351,6 +352,21 @@
 		reset_deassert(&reset);
 	}
 
+	/* get usbphyc regulator */
+	ret = device_get_supply_regulator(dev, "vdda1v1-supply",
+					  &usbphyc->vdda1v1);
+	if (ret) {
+		dev_err(dev, "Can't get vdda1v1-supply regulator\n");
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "vdda1v8-supply",
+					  &usbphyc->vdda1v8);
+	if (ret) {
+		dev_err(dev, "Can't get vdda1v8-supply regulator\n");
+		return ret;
+	}
+
 	/*
 	 * parse all PHY subnodes in order to populate regulator associated
 	 * to each PHY port
@@ -359,7 +375,6 @@
 	for (i = 0; i < MAX_PHYS; i++) {
 		struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
 
-		usbphyc_phy->index = i;
 		usbphyc_phy->init = false;
 		usbphyc_phy->powered = false;
 		ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
@@ -367,16 +382,6 @@
 		if (ret)
 			return ret;
 
-		ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v1-supply",
-						  &usbphyc_phy->vdda1v1);
-		if (ret)
-			return ret;
-
-		ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v8-supply",
-						  &usbphyc_phy->vdda1v8);
-		if (ret)
-			return ret;
-
 		node = dev_read_next_subnode(node);
 	}
 
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index b2acfcd..cb83126 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -24,9 +24,39 @@
 #define NR_BANKS		8
 
 struct socfpga_reset_data {
-	void __iomem *membase;
+	void __iomem *modrst_base;
 };
 
+/*
+ * For compatibility with Kernels that don't support peripheral reset, this
+ * driver can keep the old behaviour of not asserting peripheral reset before
+ * starting the OS and deasserting all peripheral resets (enabling all
+ * peripherals).
+ *
+ * For that, the reset driver checks the environment variable
+ * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
+ * reset again once taken out of reset and all peripherals in 'permodrst' are
+ * taken out of reset before booting into the OS.
+ * Note that this should be required for gen5 systems only that are running
+ * Linux kernels without proper peripheral reset support for all drivers used.
+ */
+static bool socfpga_reset_keep_enabled(void)
+{
+#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
+	const char *env_str;
+	long val;
+
+	env_str = env_get("socfpga_legacy_reset_compat");
+	if (env_str) {
+		val = simple_strtol(env_str, NULL, 0);
+		if (val == 1)
+			return true;
+	}
+#endif
+
+	return false;
+}
+
 static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
 {
 	struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
@@ -35,7 +65,7 @@
 	int bank = id / (reg_width * BITS_PER_BYTE);
 	int offset = id % (reg_width * BITS_PER_BYTE);
 
-	setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
+	setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
 	return 0;
 }
 
@@ -47,7 +77,7 @@
 	int bank = id / (reg_width * BITS_PER_BYTE);
 	int offset = id % (reg_width * BITS_PER_BYTE);
 
-	clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
+	clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
 	return 0;
 }
 
@@ -80,11 +110,24 @@
 	const void *blob = gd->fdt_blob;
 	int node = dev_of_offset(dev);
 	u32 modrst_offset;
+	void __iomem *membase;
 
-	data->membase = devfdt_get_addr_ptr(dev);
+	membase = devfdt_get_addr_ptr(dev);
 
 	modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10);
-	data->membase += modrst_offset;
+	data->modrst_base = membase + modrst_offset;
+
+	return 0;
+}
+
+static int socfpga_reset_remove(struct udevice *dev)
+{
+	struct socfpga_reset_data *data = dev_get_priv(dev);
+
+	if (socfpga_reset_keep_enabled()) {
+		puts("Deasserting all peripheral resets\n");
+		writel(0, data->modrst_base + 4);
+	}
 
 	return 0;
 }
@@ -101,4 +144,6 @@
 	.probe = socfpga_reset_probe,
 	.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
 	.ops = &socfpga_reset_ops,
+	.remove = socfpga_reset_remove,
+	.flags	= DM_FLAG_OS_PREPARE,
 };
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a700f24..fb794ad 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -259,6 +259,13 @@
 	  be used to access SPI chips on platforms embedding this
 	  NVIDIA Tegra210 IP core.
 
+config TI_QSPI
+	bool "TI QSPI driver"
+	imply TI_EDMA3
+	help
+	  Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
+	  This driver support spi flash single, quad and memory reads.
+
 config XILINX_SPI
 	bool "Xilinx SPI driver"
 	help
@@ -346,12 +353,6 @@
 	  Enable the Renesas Quad SPI controller driver. This driver can be
 	  used on Renesas SoCs.
 
-config TI_QSPI
-	bool "TI QSPI driver"
-	help
-	  Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
-	  This driver support spi flash single, quad and memory reads.
-
 config KIRKWOOD_SPI
 	bool "Marvell Kirkwood SPI Driver"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 01907be..8be9a4b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -9,6 +9,7 @@
 obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
 obj-$(CONFIG_SOFT_SPI) += soft_spi.o
 obj-$(CONFIG_SPI_MEM) += spi-mem.o
+obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 else
 obj-y += spi.o
 obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
@@ -56,7 +57,6 @@
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
-obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
 obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index efdb178..41c8700 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -8,6 +8,7 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
+#include <reset.h>
 #include <spi.h>
 #include <linux/errno.h>
 #include "cadence_qspi.h"
@@ -154,10 +155,17 @@
 {
 	struct cadence_spi_platdata *plat = bus->platdata;
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
+	int ret;
 
 	priv->regbase = plat->regbase;
 	priv->ahbbase = plat->ahbbase;
 
+	ret = reset_get_bulk(bus, &priv->resets);
+	if (ret)
+		dev_warn(bus, "Can't get reset: %d\n", ret);
+	else
+		reset_deassert_bulk(&priv->resets);
+
 	if (!priv->qspi_is_init) {
 		cadence_qspi_apb_controller_init(plat);
 		priv->qspi_is_init = 1;
@@ -166,6 +174,13 @@
 	return 0;
 }
 
+static int cadence_spi_remove(struct udevice *dev)
+{
+	struct cadence_spi_priv *priv = dev_get_priv(dev);
+
+	return reset_release_bulk(&priv->resets);
+}
+
 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 {
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
@@ -342,4 +357,6 @@
 	.platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
 	.priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
 	.probe = cadence_spi_probe,
+	.remove = cadence_spi_remove,
+	.flags = DM_FLAG_OS_PREPARE,
 };
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index b491407..20cceca 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -7,6 +7,8 @@
 #ifndef __CADENCE_QSPI_H__
 #define __CADENCE_QSPI_H__
 
+#include <reset.h>
+
 #define CQSPI_IS_ADDR(cmd_len)		(cmd_len > 1 ? 1 : 0)
 
 #define CQSPI_NO_DECODER_MAX_CS		4
@@ -42,6 +44,8 @@
 	unsigned int	qspi_calibrated_hz;
 	unsigned int	qspi_calibrated_cs;
 	unsigned int	previous_hz;
+
+	struct reset_ctl_bulk resets;
 };
 
 /* Functions call declaration */
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 2dcce66..77fa17e 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -10,6 +10,7 @@
 #include <asm/arch/omap.h>
 #include <malloc.h>
 #include <spi.h>
+#include <spi-mem.h>
 #include <dm.h>
 #include <asm/gpio.h>
 #include <asm/omap_gpio.h>
@@ -40,7 +41,6 @@
 #define QSPI_INVAL                      (4 << 16)
 #define QSPI_RD_QUAD                    (7 << 16)
 /* device control */
-#define QSPI_DD(m, n)                   (m << (3 + n*8))
 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
 #define QSPI_CKPOL(n)                   (1 << (n*8))
@@ -52,22 +52,12 @@
 #define MM_SWITCH                       0x01
 #define MEM_CS(cs)                      ((cs + 1) << 8)
 #define MEM_CS_UNSELECT                 0xfffff8ff
-#define MMAP_START_ADDR_DRA		0x5c000000
-#define MMAP_START_ADDR_AM43x		0x30000000
-#define CORE_CTRL_IO                    0x4a002558
 
-#define QSPI_CMD_READ                   (0x3 << 0)
-#define QSPI_CMD_READ_DUAL		(0x6b << 0)
-#define QSPI_CMD_READ_QUAD              (0x6c << 0)
-#define QSPI_CMD_READ_FAST              (0x0b << 0)
-#define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
-#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
-#define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
-#define QSPI_CMD_WRITE                  (0x12 << 16)
-#define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
+#define QSPI_SETUP0_ADDR_SHIFT		(8)
+#define QSPI_SETUP0_DBITS_SHIFT		(10)
 
 /* ti qspi register set */
 struct ti_qspi_regs {
@@ -98,13 +88,10 @@
 
 /* ti qspi priv */
 struct ti_qspi_priv {
-#ifndef CONFIG_DM_SPI
-	struct spi_slave slave;
-#else
 	void *memory_map;
+	size_t mmap_size;
 	uint max_hz;
 	u32 num_cs;
-#endif
 	struct ti_qspi_regs *base;
 	void *ctrl_mod_mmap;
 	ulong fclk;
@@ -113,8 +100,9 @@
 	u32 dc;
 };
 
-static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
+static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 {
+	struct ti_qspi_priv *priv = dev_get_priv(bus);
 	uint clk_div;
 
 	if (!hz)
@@ -133,6 +121,8 @@
 	       &priv->base->clk_ctrl);
 	/* enable SCLK and program the clk divider */
 	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
+
+	return 0;
 }
 
 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
@@ -142,38 +132,6 @@
 	readl(&priv->base->cmd);
 }
 
-static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
-{
-	priv->dc = 0;
-	if (mode & SPI_CPHA)
-		priv->dc |= QSPI_CKPHA(0);
-	if (mode & SPI_CPOL)
-		priv->dc |= QSPI_CKPOL(0);
-	if (mode & SPI_CS_HIGH)
-		priv->dc |= QSPI_CSPOL(0);
-
-	return 0;
-}
-
-static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
-{
-	writel(priv->dc, &priv->base->dc);
-	writel(0, &priv->base->cmd);
-	writel(0, &priv->base->data);
-
-	priv->dc <<= cs * 8;
-	writel(priv->dc, &priv->base->dc);
-
-	return 0;
-}
-
-static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
-{
-	writel(0, &priv->base->dc);
-	writel(0, &priv->base->cmd);
-	writel(0, &priv->base->data);
-}
-
 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 {
 	u32 val;
@@ -186,27 +144,25 @@
 	writel(val, ctrl_mod_mmap);
 }
 
-static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
-			const void *dout, void *din, unsigned long flags,
-			u32 cs)
+static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+			const void *dout, void *din, unsigned long flags)
 {
+	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+	struct ti_qspi_priv *priv;
+	struct udevice *bus;
 	uint words = bitlen >> 3; /* fixed 8-bit word length */
 	const uchar *txp = dout;
 	uchar *rxp = din;
 	uint status;
 	int timeout;
+	unsigned int cs = slave->cs;
 
-	/* Setup mmap flags */
-	if (flags & SPI_XFER_MMAP) {
-		writel(MM_SWITCH, &priv->base->memswitch);
-		if (priv->ctrl_mod_mmap)
-			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
-		return 0;
-	} else if (flags & SPI_XFER_MMAP_END) {
-		writel(~MM_SWITCH, &priv->base->memswitch);
-		if (priv->ctrl_mod_mmap)
-			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
-		return 0;
+	bus = dev->parent;
+	priv = dev_get_priv(bus);
+
+	if (cs > priv->num_cs) {
+		debug("invalid qspi chip select\n");
+		return -EINVAL;
 	}
 
 	if (bitlen == 0)
@@ -294,9 +250,9 @@
 }
 
 /* TODO: control from sf layer to here through dm-spi */
-#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
-void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
 {
+#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 	unsigned int			addr = (unsigned int) (data);
 	unsigned int			edma_slot_num = 1;
 
@@ -311,187 +267,85 @@
 
 	/* disable edma3 clocks */
 	disable_edma3_clocks();
+#else
+	memcpy_fromio(data, offset, len);
+#endif
 
 	*((unsigned int *)offset) += len;
 }
-#endif
 
-#ifndef CONFIG_DM_SPI
-
-static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
+static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
+				    u8 data_nbits, u8 addr_width,
+				    u8 dummy_bytes)
 {
-	return container_of(slave, struct ti_qspi_priv, slave);
-}
+	u32 memval = opcode;
 
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	/* CS handled in xfer */
-	return;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-	ti_qspi_cs_deactivate(priv);
-}
-
-void spi_init(void)
-{
-	/* nothing to do */
-}
-
-static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
-{
-	u32 memval = 0;
-
-#ifdef CONFIG_QSPI_QUAD_SUPPORT
-	struct spi_slave *slave = &priv->slave;
-	memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
-			QSPI_SETUP0_NUM_D_BYTES_8_BITS |
-			QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
-			QSPI_NUM_DUMMY_BITS);
-	slave->mode |= SPI_RX_QUAD;
-#else
-	memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
-			QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
-			QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
-			QSPI_NUM_DUMMY_BITS;
-#endif
-
-	writel(memval, &priv->base->setup0);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
-{
-	struct ti_qspi_priv *priv;
-
-#ifdef CONFIG_AM43XX
-	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
-	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
-#endif
-
-	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
-	if (!priv) {
-		printf("SPI_error: Fail to allocate ti_qspi_priv\n");
-		return NULL;
-	}
-
-	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
-	priv->mode = mode;
-#if defined(CONFIG_DRA7XX)
-	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
-	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
-	priv->fclk = QSPI_DRA7XX_FCLK;
-#else
-	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
-	priv->fclk = QSPI_FCLK;
-#endif
-
-	ti_spi_set_speed(priv, max_hz);
-
-#ifdef CONFIG_TI_SPI_MMAP
-	ti_spi_setup_spi_register(priv);
-#endif
-
-	return &priv->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-	free(priv);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
-	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
-	__ti_qspi_set_mode(priv, priv->mode);
-	return __ti_qspi_claim_bus(priv, priv->slave.cs);
-}
-void spi_release_bus(struct spi_slave *slave)
-{
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
-	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
-	__ti_qspi_release_bus(priv);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-	     void *din, unsigned long flags)
-{
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
-	debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
-	      priv->slave.bus, priv->slave.cs, bitlen, flags);
-	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
-}
-
-#else /* CONFIG_DM_SPI */
-
-static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
-				      struct spi_slave *slave,
-				      bool enable)
-{
-	u32 memval;
-	u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
-
-	if (!enable) {
-		writel(0, &priv->base->setup0);
-		return;
-	}
-
-	memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
-
-	switch (mode) {
-	case SPI_RX_QUAD:
-		memval |= QSPI_CMD_READ_QUAD;
-		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+	switch (data_nbits) {
+	case 4:
 		memval |= QSPI_SETUP0_READ_QUAD;
-		slave->mode |= SPI_RX_QUAD;
 		break;
-	case SPI_RX_DUAL:
-		memval |= QSPI_CMD_READ_DUAL;
-		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+	case 2:
 		memval |= QSPI_SETUP0_READ_DUAL;
 		break;
 	default:
-		memval |= QSPI_CMD_READ;
-		memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
 		memval |= QSPI_SETUP0_READ_NORMAL;
 		break;
 	}
 
+	memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
+		   dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
+
 	writel(memval, &priv->base->setup0);
 }
 
-
-static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
-{
-	struct ti_qspi_priv *priv = dev_get_priv(bus);
-
-	ti_spi_set_speed(priv, max_hz);
-
-	return 0;
-}
-
 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 {
 	struct ti_qspi_priv *priv = dev_get_priv(bus);
-	return __ti_qspi_set_mode(priv, mode);
+
+	priv->dc = 0;
+	if (mode & SPI_CPHA)
+		priv->dc |= QSPI_CKPHA(0);
+	if (mode & SPI_CPOL)
+		priv->dc |= QSPI_CKPOL(0);
+	if (mode & SPI_CS_HIGH)
+		priv->dc |= QSPI_CSPOL(0);
+
+	return 0;
+}
+
+static int ti_qspi_exec_mem_op(struct spi_slave *slave,
+			       const struct spi_mem_op *op)
+{
+	struct ti_qspi_priv *priv;
+	struct udevice *bus;
+
+	bus = slave->dev->parent;
+	priv = dev_get_priv(bus);
+	u32 from = 0;
+	int ret = 0;
+
+	/* Only optimize read path. */
+	if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
+	    !op->addr.nbytes || op->addr.nbytes > 4)
+		return -ENOTSUPP;
+
+	/* Address exceeds MMIO window size, fall back to regular mode. */
+	from = op->addr.val;
+	if (from + op->data.nbytes > priv->mmap_size)
+		return -ENOTSUPP;
+
+	ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
+				op->addr.nbytes, op->dummy.nbytes);
+
+	ti_qspi_copy_mmap((void *)op->data.buf.in,
+			  (void *)priv->memory_map + from, op->data.nbytes);
+
+	return ret;
 }
 
 static int ti_qspi_claim_bus(struct udevice *dev)
 {
 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
-	struct spi_slave *slave = dev_get_parent_priv(dev);
 	struct ti_qspi_priv *priv;
 	struct udevice *bus;
 
@@ -503,42 +357,41 @@
 		return -EINVAL;
 	}
 
-	__ti_qspi_setup_memorymap(priv, slave, true);
+	writel(MM_SWITCH, &priv->base->memswitch);
+	if (priv->ctrl_mod_mmap)
+		ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
+				       slave_plat->cs, true);
 
-	return __ti_qspi_claim_bus(priv, slave_plat->cs);
-}
+	writel(priv->dc, &priv->base->dc);
+	writel(0, &priv->base->cmd);
+	writel(0, &priv->base->data);
 
-static int ti_qspi_release_bus(struct udevice *dev)
-{
-	struct spi_slave *slave = dev_get_parent_priv(dev);
-	struct ti_qspi_priv *priv;
-	struct udevice *bus;
-
-	bus = dev->parent;
-	priv = dev_get_priv(bus);
-
-	__ti_qspi_setup_memorymap(priv, slave, false);
-	__ti_qspi_release_bus(priv);
+	priv->dc <<= slave_plat->cs * 8;
+	writel(priv->dc, &priv->base->dc);
 
 	return 0;
 }
 
-static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
-			const void *dout, void *din, unsigned long flags)
+static int ti_qspi_release_bus(struct udevice *dev)
 {
-	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 	struct ti_qspi_priv *priv;
 	struct udevice *bus;
 
 	bus = dev->parent;
 	priv = dev_get_priv(bus);
 
-	if (slave->cs > priv->num_cs) {
-		debug("invalid qspi chip select\n");
-		return -EINVAL;
-	}
+	writel(~MM_SWITCH, &priv->base->memswitch);
+	if (priv->ctrl_mod_mmap)
+		ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
+				       slave_plat->cs, false);
 
-	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
+	writel(0, &priv->base->dc);
+	writel(0, &priv->base->cmd);
+	writel(0, &priv->base->data);
+	writel(0, &priv->base->setup0);
+
+	return 0;
 }
 
 static int ti_qspi_probe(struct udevice *bus)
@@ -594,12 +447,15 @@
 	struct ti_qspi_priv *priv = dev_get_priv(bus);
 	const void *blob = gd->fdt_blob;
 	int node = dev_of_offset(bus);
+	fdt_addr_t mmap_addr;
+	fdt_addr_t mmap_size;
 
 	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 	priv->base = map_physmem(devfdt_get_addr(bus),
 				 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
-	priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
-				       MAP_NOCACHE);
+	mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
+	priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
+	priv->mmap_size = mmap_size;
 
 	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 	if (priv->max_hz < 0) {
@@ -614,15 +470,9 @@
 	return 0;
 }
 
-static int ti_qspi_child_pre_probe(struct udevice *dev)
-{
-	struct spi_slave *slave = dev_get_parent_priv(dev);
-	struct udevice *bus = dev_get_parent(dev);
-	struct ti_qspi_priv *priv = dev_get_priv(bus);
-
-	slave->memory_map = priv->memory_map;
-	return 0;
-}
+static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
+	.exec_op = ti_qspi_exec_mem_op,
+};
 
 static const struct dm_spi_ops ti_qspi_ops = {
 	.claim_bus	= ti_qspi_claim_bus,
@@ -630,6 +480,7 @@
 	.xfer		= ti_qspi_xfer,
 	.set_speed	= ti_qspi_set_speed,
 	.set_mode	= ti_qspi_set_mode,
+	.mem_ops        = &ti_qspi_mem_ops,
 };
 
 static const struct udevice_id ti_qspi_ids[] = {
@@ -646,6 +497,4 @@
 	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 	.probe	= ti_qspi_probe,
-	.child_pre_probe = ti_qspi_child_pre_probe,
 };
-#endif /* CONFIG_DM_SPI */
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index da9413c..04ea42c 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -267,7 +267,7 @@
 		zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 		tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 				TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
-	} else if (reqhz < GQSPI_FREQ_100MHZ) {
+	} else if (reqhz <= GQSPI_FREQ_100MHZ) {
 		zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 		tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 				TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
@@ -277,7 +277,7 @@
 		datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 				| (GQSPI_DATA_DLY_ADJ_VALUE <<
 					GQSPI_DATA_DLY_ADJ_SHIFT));
-	} else if (reqhz < GQSPI_FREQ_150MHZ) {
+	} else if (reqhz <= GQSPI_FREQ_150MHZ) {
 		lpbkdlyadj = readl(&regs->lpbkdly);
 		lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
 				GQSPI_LPBK_DLY_ADJ_DLY_0);
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 085bfb0..cb48801 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -32,7 +32,7 @@
 	 * requires the count to be incrementing. Invert the
 	 * result.
 	 */
-	*count = ~readl(priv->regs + DW_APB_CURR_VAL);
+	*count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
 
 	return 0;
 }
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index 3c7ad03..494ab53 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -18,11 +18,17 @@
  */
 #undef DEBUG
 #include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <malloc.h>
+#include <reset.h>
+
 #include <linux/errno.h>
 #include <linux/list.h>
-#include <malloc.h>
 
 #include <linux/usb/ch9.h>
+#include <linux/usb/otg.h>
 #include <linux/usb/gadget.h>
 
 #include <asm/byteorder.h>
@@ -31,6 +37,8 @@
 
 #include <asm/mach-types.h>
 
+#include <power/regulator.h>
+
 #include "dwc2_udc_otg_regs.h"
 #include "dwc2_udc_otg_priv.h"
 
@@ -140,7 +148,6 @@
 
 /***********************************************************/
 
-void __iomem		*regs_otg;
 struct dwc2_usbotg_reg *reg;
 
 bool dfu_usb_get_reset(void)
@@ -223,6 +230,7 @@
 	return 0;
 }
 
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
 /*
   Register entry point for the peripheral controller driver.
 */
@@ -297,6 +305,54 @@
 	udc_disable(dev);
 	return 0;
 }
+#else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
+
+static int dwc2_gadget_start(struct usb_gadget *g,
+			     struct usb_gadget_driver *driver)
+{
+	struct dwc2_udc *dev = the_controller;
+
+	debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
+
+	if (!driver ||
+	    (driver->speed != USB_SPEED_FULL &&
+	     driver->speed != USB_SPEED_HIGH) ||
+	    !driver->bind || !driver->disconnect || !driver->setup)
+		return -EINVAL;
+
+	if (!dev)
+		return -ENODEV;
+
+	if (dev->driver)
+		return -EBUSY;
+
+	/* first hook up the driver ... */
+	dev->driver = driver;
+
+	debug_cond(DEBUG_SETUP != 0,
+		   "Registered gadget driver %s\n", dev->gadget.name);
+	return udc_enable(dev);
+}
+
+static int dwc2_gadget_stop(struct usb_gadget *g)
+{
+	struct dwc2_udc *dev = the_controller;
+
+	if (!dev)
+		return -ENODEV;
+
+	if (!dev->driver)
+		return -EINVAL;
+
+	dev->driver = 0;
+	stop_activity(dev, dev->driver);
+
+	udc_disable(dev);
+
+	return 0;
+}
+
+#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 
 /*
  *	done - retire a request; caller blocked irqs
@@ -400,6 +456,8 @@
 	unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
 	uint32_t dflt_gusbcfg;
 	uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
+	u32 max_hw_ep;
+	int pdata_hw_ep;
 
 	debug("Reseting OTG controller\n");
 
@@ -482,10 +540,23 @@
 	writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
 	       &reg->gnptxfsiz);
 
-	for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
-		writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
-			tx_fifo_sz << 16, &reg->dieptxf[i-1]);
+	/* retrieve the number of IN Endpoints (excluding ep0) */
+	max_hw_ep = (readl(&reg->ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >>
+		    GHWCFG4_NUM_IN_EPS_SHIFT;
+	pdata_hw_ep = dev->pdata->tx_fifo_sz_nb;
 
+	/* tx_fifo_sz_nb should equal to number of IN Endpoint */
+	if (pdata_hw_ep && max_hw_ep != pdata_hw_ep)
+		pr_warn("Got %d hw endpoint but %d tx-fifo-size in array !!\n",
+			max_hw_ep, pdata_hw_ep);
+
+	for (i = 0; i < max_hw_ep; i++) {
+		if (pdata_hw_ep)
+			tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i];
+
+		writel((rx_fifo_sz + np_tx_fifo_sz + (tx_fifo_sz * i)) |
+			tx_fifo_sz << 16, &reg->dieptxf[i]);
+	}
 	/* Flush the RX FIFO */
 	writel(RX_FIFO_FLUSH, &reg->grstctl);
 	while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
@@ -731,6 +802,10 @@
 
 static const struct usb_gadget_ops dwc2_udc_ops = {
 	/* current versions must always be self-powered */
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+	.udc_start		= dwc2_gadget_start,
+	.udc_stop		= dwc2_gadget_stop,
+#endif
 };
 
 static struct dwc2_udc memory = {
@@ -818,8 +893,6 @@
 
 	reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
 
-	/* regs_otg = (void *)pdata->regs_otg; */
-
 	dev->gadget.is_dualspeed = 1;	/* Hack only*/
 	dev->gadget.is_otg = 0;
 	dev->gadget.is_a_peripheral = 0;
@@ -844,12 +917,311 @@
 	return retval;
 }
 
-int usb_gadget_handle_interrupts(int index)
+int dwc2_udc_handle_interrupt(void)
 {
 	u32 intr_status = readl(&reg->gintsts);
 	u32 gintmsk = readl(&reg->gintmsk);
 
 	if (intr_status & gintmsk)
 		return dwc2_udc_irq(1, (void *)the_controller);
+
 	return 0;
 }
+
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
+
+int usb_gadget_handle_interrupts(int index)
+{
+	return dwc2_udc_handle_interrupt();
+}
+
+#else /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
+
+struct dwc2_priv_data {
+	struct clk_bulk		clks;
+	struct reset_ctl_bulk	resets;
+	struct phy *phys;
+	int num_phys;
+	struct udevice *usb33d_supply;
+};
+
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+	return dwc2_udc_handle_interrupt();
+}
+
+int dwc2_phy_setup(struct udevice *dev, struct phy **array, int *num_phys)
+{
+	int i, ret, count;
+	struct phy *usb_phys;
+
+	/* Return if no phy declared */
+	if (!dev_read_prop(dev, "phys", NULL))
+		return 0;
+
+	count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
+	if (count <= 0)
+		return count;
+
+	usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
+				GFP_KERNEL);
+	if (!usb_phys)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
+		if (ret && ret != -ENOENT) {
+			dev_err(dev, "Failed to get USB PHY%d for %s\n",
+				i, dev->name);
+			return ret;
+		}
+	}
+
+	for (i = 0; i < count; i++) {
+		ret = generic_phy_init(&usb_phys[i]);
+		if (ret) {
+			dev_err(dev, "Can't init USB PHY%d for %s\n",
+				i, dev->name);
+			goto phys_init_err;
+		}
+	}
+
+	for (i = 0; i < count; i++) {
+		ret = generic_phy_power_on(&usb_phys[i]);
+		if (ret) {
+			dev_err(dev, "Can't power USB PHY%d for %s\n",
+				i, dev->name);
+			goto phys_poweron_err;
+		}
+	}
+
+	*array = usb_phys;
+	*num_phys =  count;
+
+	return 0;
+
+phys_poweron_err:
+	for (i = count - 1; i >= 0; i--)
+		generic_phy_power_off(&usb_phys[i]);
+
+	for (i = 0; i < count; i++)
+		generic_phy_exit(&usb_phys[i]);
+
+	return ret;
+
+phys_init_err:
+	for (; i >= 0; i--)
+		generic_phy_exit(&usb_phys[i]);
+
+	return ret;
+}
+
+void dwc2_phy_shutdown(struct udevice *dev, struct phy *usb_phys, int num_phys)
+{
+	int i, ret;
+
+	for (i = 0; i < num_phys; i++) {
+		if (!generic_phy_valid(&usb_phys[i]))
+			continue;
+
+		ret = generic_phy_power_off(&usb_phys[i]);
+		ret |= generic_phy_exit(&usb_phys[i]);
+		if (ret) {
+			dev_err(dev, "Can't shutdown USB PHY%d for %s\n",
+				i, dev->name);
+		}
+	}
+}
+
+static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev)
+{
+	struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+	int node = dev_of_offset(dev);
+	ulong drvdata;
+	void (*set_params)(struct dwc2_plat_otg_data *data);
+
+	if (usb_get_dr_mode(node) != USB_DR_MODE_PERIPHERAL) {
+		dev_dbg(dev, "Invalid mode\n");
+		return -ENODEV;
+	}
+
+	platdata->regs_otg = dev_read_addr(dev);
+
+	platdata->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
+	platdata->np_tx_fifo_sz = dev_read_u32_default(dev,
+						       "g-np-tx-fifo-size", 0);
+	platdata->tx_fifo_sz = dev_read_u32_default(dev, "g-tx-fifo-size", 0);
+
+	platdata->force_b_session_valid =
+		dev_read_bool(dev, "u-boot,force-b-session-valid");
+
+	/* force platdata according compatible */
+	drvdata = dev_get_driver_data(dev);
+	if (drvdata) {
+		set_params = (void *)drvdata;
+		set_params(platdata);
+	}
+
+	return 0;
+}
+
+static void dwc2_set_stm32mp1_hsotg_params(struct dwc2_plat_otg_data *p)
+{
+	p->activate_stm_id_vb_detection = true;
+	p->usb_gusbcfg =
+		0 << 15		/* PHY Low Power Clock sel*/
+		| 0x9 << 10	/* USB Turnaround time (0x9 for HS phy) */
+		| 0 << 9	/* [0:HNP disable,1:HNP enable]*/
+		| 0 << 8	/* [0:SRP disable 1:SRP enable]*/
+		| 0 << 6	/* 0: high speed utmi+, 1: full speed serial*/
+		| 0x7 << 0;	/* FS timeout calibration**/
+
+	if (p->force_b_session_valid)
+		p->usb_gusbcfg |= 1 << 30; /* FDMOD: Force device mode */
+}
+
+static int dwc2_udc_otg_reset_init(struct udevice *dev,
+				   struct reset_ctl_bulk *resets)
+{
+	int ret;
+
+	ret = reset_get_bulk(dev, resets);
+	if (ret == -ENOTSUPP)
+		return 0;
+
+	if (ret)
+		return ret;
+
+	ret = reset_assert_bulk(resets);
+
+	if (!ret) {
+		udelay(2);
+		ret = reset_deassert_bulk(resets);
+	}
+	if (ret) {
+		reset_release_bulk(resets);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dwc2_udc_otg_clk_init(struct udevice *dev,
+				 struct clk_bulk *clks)
+{
+	int ret;
+
+	ret = clk_get_bulk(dev, clks);
+	if (ret == -ENOSYS)
+		return 0;
+
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(clks);
+	if (ret) {
+		clk_release_bulk(clks);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dwc2_udc_otg_probe(struct udevice *dev)
+{
+	struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+	struct dwc2_priv_data *priv = dev_get_priv(dev);
+	struct dwc2_usbotg_reg *usbotg_reg =
+		(struct dwc2_usbotg_reg *)platdata->regs_otg;
+	int ret;
+
+	ret = dwc2_udc_otg_clk_init(dev, &priv->clks);
+	if (ret)
+		return ret;
+
+	ret = dwc2_udc_otg_reset_init(dev, &priv->resets);
+	if (ret)
+		return ret;
+
+	ret = dwc2_phy_setup(dev, &priv->phys, &priv->num_phys);
+	if (ret)
+		return ret;
+
+	if (CONFIG_IS_ENABLED(DM_REGULATOR) &&
+	    platdata->activate_stm_id_vb_detection &&
+	    !platdata->force_b_session_valid) {
+		ret = device_get_supply_regulator(dev, "usb33d-supply",
+						  &priv->usb33d_supply);
+		if (ret) {
+			dev_err(dev, "can't get voltage level detector supply\n");
+			return ret;
+		}
+		ret = regulator_set_enable(priv->usb33d_supply, true);
+		if (ret) {
+			dev_err(dev, "can't enable voltage level detector supply\n");
+			return ret;
+		}
+		/* Enable vbus sensing */
+		setbits_le32(&usbotg_reg->ggpio,
+			     GGPIO_STM32_OTG_GCCFG_VBDEN |
+			     GGPIO_STM32_OTG_GCCFG_IDEN);
+	}
+
+	if (platdata->force_b_session_valid)
+		/* Override B session bits : value and enable */
+		setbits_le32(&usbotg_reg->gotgctl,
+			     A_VALOEN | A_VALOVAL | B_VALOEN | B_VALOVAL);
+
+	ret = dwc2_udc_probe(platdata);
+	if (ret)
+		return ret;
+
+	the_controller->driver = 0;
+
+	ret = usb_add_gadget_udc((struct device *)dev, &the_controller->gadget);
+
+	return ret;
+}
+
+static int dwc2_udc_otg_remove(struct udevice *dev)
+{
+	struct dwc2_priv_data *priv = dev_get_priv(dev);
+
+	usb_del_gadget_udc(&the_controller->gadget);
+
+	reset_release_bulk(&priv->resets);
+
+	clk_release_bulk(&priv->clks);
+
+	dwc2_phy_shutdown(dev, priv->phys, priv->num_phys);
+
+	return dm_scan_fdt_dev(dev);
+}
+
+static const struct udevice_id dwc2_udc_otg_ids[] = {
+	{ .compatible = "snps,dwc2" },
+	{ .compatible = "st,stm32mp1-hsotg",
+	  .data = (ulong)dwc2_set_stm32mp1_hsotg_params },
+	{},
+};
+
+U_BOOT_DRIVER(dwc2_udc_otg) = {
+	.name	= "dwc2-udc-otg",
+	.id	= UCLASS_USB_GADGET_GENERIC,
+	.of_match = dwc2_udc_otg_ids,
+	.ofdata_to_platdata = dwc2_udc_otg_ofdata_to_platdata,
+	.probe = dwc2_udc_otg_probe,
+	.remove = dwc2_udc_otg_remove,
+	.platdata_auto_alloc_size = sizeof(struct dwc2_plat_otg_data),
+	.priv_auto_alloc_size = sizeof(struct dwc2_priv_data),
+};
+
+int dwc2_udc_B_session_valid(struct udevice *dev)
+{
+	struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+	struct dwc2_usbotg_reg *usbotg_reg =
+		(struct dwc2_usbotg_reg *)platdata->regs_otg;
+
+	return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID;
+}
+#endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
diff --git a/drivers/usb/gadget/dwc2_udc_otg_priv.h b/drivers/usb/gadget/dwc2_udc_otg_priv.h
index aaa9018..e72b22a 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_priv.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_priv.h
@@ -23,7 +23,6 @@
 #define EP_FIFO_SIZE2		1024
 /* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
 #define DWC2_MAX_ENDPOINTS	4
-#define DWC2_MAX_HW_ENDPOINTS	16
 
 #define WAIT_FOR_SETUP          0
 #define DATA_STATE_XMIT         1
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h
index a1829b3..434db5b 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_regs.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
@@ -60,22 +60,26 @@
 	u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
 	u32 grxfsiz; /* Receive FIFO Size */
 	u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
-	u8  res1[216];
+	u8  res0[12];
+	u32 ggpio;     /* 0x038 */
+	u8  res1[20];
+	u32 ghwcfg4; /* User HW Config4 */
+	u8  res2[176];
 	u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
-	u8  res2[1728];
+	u8  res3[1728];
 	/* Device Configuration */
 	u32 dcfg; /* Device Configuration Register */
 	u32 dctl; /* Device Control */
 	u32 dsts; /* Device Status */
-	u8  res3[4];
+	u8  res4[4];
 	u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
 	u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
 	u32 daint; /* Device All Endpoints Interrupt */
 	u32 daintmsk; /* Device All Endpoints Interrupt Mask */
-	u8  res4[224];
+	u8  res5[224];
 	struct dwc2_dev_in_endp in_endp[16];
 	struct dwc2_dev_out_endp out_endp[16];
-	u8  res5[768];
+	u8  res6[768];
 	struct ep_fifo ep[16];
 };
 
@@ -83,8 +87,15 @@
 /*definitions related to CSR setting */
 
 /* DWC2_UDC_OTG_GOTGCTL */
-#define B_SESSION_VALID		(0x1<<19)
-#define A_SESSION_VALID		(0x1<<18)
+#define B_SESSION_VALID			BIT(19)
+#define A_SESSION_VALID			BIT(18)
+#define B_VALOVAL			BIT(7)
+#define B_VALOEN			BIT(6)
+#define A_VALOVAL			BIT(5)
+#define A_VALOEN			BIT(4)
+
+/* DWC2_UDC_OTG_GOTINT */
+#define GOTGINT_SES_END_DET		(1<<2)
 
 /* DWC2_UDC_OTG_GAHBCFG */
 #define PTXFE_HALF			(0<<8)
@@ -118,6 +129,7 @@
 #define INT_NP_TX_FIFO_EMPTY		(0x1<<5)
 #define INT_RX_FIFO_NOT_EMPTY		(0x1<<4)
 #define INT_SOF			(0x1<<3)
+#define INT_OTG			(0x1<<2)
 #define INT_DEV_MODE			(0x0<<0)
 #define INT_HOST_MODE			(0x1<<1)
 #define INT_GOUTNakEff			(0x01<<7)
@@ -246,7 +258,7 @@
 
 /* Masks definitions */
 #define GINTMSK_INIT	(INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
-			| INT_RESET | INT_SUSPEND)
+			| INT_RESET | INT_SUSPEND | INT_OTG)
 #define DOEPMSK_INIT	(CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
 #define DIEPMSK_INIT	(NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
 #define GAHBCFG_INIT	(PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
@@ -269,4 +281,13 @@
 /* Device ALL Endpoints Interrupt Register (DAINT) */
 #define DAINT_IN_EP_INT(x)                        (x << 0)
 #define DAINT_OUT_EP_INT(x)                       (x << 16)
+
+/* User HW Config4 */
+#define GHWCFG4_NUM_IN_EPS_MASK		(0xf << 26)
+#define GHWCFG4_NUM_IN_EPS_SHIFT	26
+
+/* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */
+#define GGPIO_STM32_OTG_GCCFG_VBDEN               BIT(21)
+#define GGPIO_STM32_OTG_GCCFG_IDEN                BIT(22)
+
 #endif
diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index a75af49..7eb632d 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -467,7 +467,7 @@
 static int dwc2_udc_irq(int irq, void *_dev)
 {
 	struct dwc2_udc *dev = _dev;
-	u32 intr_status;
+	u32 intr_status, gotgint;
 	u32 usb_status, gintmsk;
 	unsigned long flags = 0;
 
@@ -521,14 +521,24 @@
 		    && dev->driver) {
 			if (dev->driver->suspend)
 				dev->driver->suspend(&dev->gadget);
+		}
+	}
 
-			/* HACK to let gadget detect disconnected state */
+	if (intr_status & INT_OTG) {
+		gotgint = readl(&reg->gotgint);
+		debug_cond(DEBUG_ISR,
+			   "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
+
+		if (gotgint & GOTGINT_SES_END_DET) {
+			debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
+			/* Let gadget detect disconnected state */
 			if (dev->driver->disconnect) {
 				spin_unlock_irqrestore(&dev->lock, flags);
 				dev->driver->disconnect(&dev->gadget);
 				spin_lock_irqsave(&dev->lock, flags);
 			}
 		}
+		writel(gotgint, &reg->gotgint);
 	}
 
 	if (intr_status & INT_RESUME) {
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index ba1e6bf..0fbc115 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -154,6 +154,13 @@
 	  Enables support for the on-chip EHCI controller on OMAP3 and later
 	  SoCs.
 
+config USB_EHCI_VF
+	bool "Support for Vybrid on-chip EHCI USB controller"
+	depends on ARCH_VF610
+	default y
+	help
+	  Enables support for the on-chip EHCI controller on Vybrid SoCs.
+
 if USB_EHCI_MX7
 
 config MXC_USB_OTG_HACTIVE
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index f8f2205..75005cc 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -21,6 +21,7 @@
 config USB_MUSB_TI
 	bool "Enable TI OTG USB controller"
 	depends on DM_USB
+	select USB_MUSB_DSPS
 	default n
 	help
 	  Say y here to enable support for the dual role high
@@ -54,6 +55,15 @@
 	Say y here to enable support for the sunxi OTG / DRC USB controller
 	used on almost all sunxi boards.
 
+config USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+	bool "Disable MUSB bulk split/combine"
+	default y
+	help
+	  On TI AM335x devices, MUSB has bulk split/combine feature enabled
+	  in the ConfigData register, but the current MUSB driver does not
+	  support it yet. Select this option to disable the feature until the
+	  driver adds the support.
+
 endif
 
 config USB_MUSB_PIO_ONLY
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2eac4b6..c3781b1 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -120,7 +120,7 @@
 
 config SYS_WHITE_ON_BLACK
 	bool "Display console as white on a black background"
-	default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || TEGRA || X86
+	default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || TEGRA || X86 || ARCH_SUNXI
 	help
 	 Normally the display is black on a white background, Enable this
 	 option to invert this, i.e. white on a black background. This can be
@@ -538,6 +538,8 @@
 
 source "drivers/video/bridge/Kconfig"
 
+source "drivers/video/imx/Kconfig"
+
 config VIDEO
 	bool "Enable legacy video support"
 	depends on !DM_VIDEO
@@ -547,13 +549,6 @@
 	  model. Video drivers typically provide a colour text console and
 	  cursor.
 
-config VIDEO_IPUV3
-	bool "i.MX IPUv3 Core video support"
-	depends on VIDEO && MX6
-	help
-	  This enables framebuffer driver for i.MX processors working
-	  on the IPUv3(Image Processing Unit) internal graphic processor.
-
 config CFB_CONSOLE
 	bool "Enable colour frame buffer console"
 	depends on VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 671f037..349a207 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -46,7 +46,7 @@
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_VIDEO_EFI) += efi.o
 obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
-obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_IPUV3) += imx/
 obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index 2cfa510..7f01ee9 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -84,7 +84,8 @@
 		return -EAGAIN;
 
 	for (row = 0; row < VIDEO_FONT_HEIGHT; row++) {
-		uchar bits = video_fontdata[ch * VIDEO_FONT_HEIGHT + row];
+		unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row;
+		uchar bits = video_fontdata[idx];
 
 		switch (vid_priv->bpix) {
 #ifdef CONFIG_VIDEO_BPP8
diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c
index f076570..71a5c5e 100644
--- a/drivers/video/console_rotate.c
+++ b/drivers/video/console_rotate.c
@@ -90,7 +90,7 @@
 	int i, col;
 	int mask = 0x80;
 	void *line;
-	uchar *pfont = video_fontdata + ch * VIDEO_FONT_HEIGHT;
+	uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT;
 
 	line = vid_priv->fb + (VID_TO_PIXEL(x_frac) + 1) *
 			vid_priv->line_length - (y + 1) * pbytes;
@@ -222,7 +222,8 @@
 			VIDEO_FONT_WIDTH - 1) * VNBYTES(vid_priv->bpix);
 
 	for (row = 0; row < VIDEO_FONT_HEIGHT; row++) {
-		uchar bits = video_fontdata[ch * VIDEO_FONT_HEIGHT + row];
+		unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row;
+		uchar bits = video_fontdata[idx];
 
 		switch (vid_priv->bpix) {
 #ifdef CONFIG_VIDEO_BPP8
@@ -348,7 +349,7 @@
 	void *line = vid_priv->fb +
 		(vid_priv->ysize - VID_TO_PIXEL(x_frac) - 1) *
 		vid_priv->line_length + y * pbytes;
-	uchar *pfont = video_fontdata + ch * VIDEO_FONT_HEIGHT;
+	uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT;
 
 	if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac)
 		return -EAGAIN;
diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig
new file mode 100644
index 0000000..c33620e
--- /dev/null
+++ b/drivers/video/imx/Kconfig
@@ -0,0 +1,8 @@
+
+config VIDEO_IPUV3
+	bool "i.MX IPUv3 Core video support"
+	depends on (VIDEO || DM_VIDEO) && (MX5 || MX6)
+	help
+	  This enables framebuffer driver for i.MX processors working
+	  on the IPUv3(Image Processing Unit) internal graphic processor.
+
diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile
new file mode 100644
index 0000000..179ea65
--- /dev/null
+++ b/drivers/video/imx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
diff --git a/drivers/video/ipu.h b/drivers/video/imx/ipu.h
similarity index 100%
rename from drivers/video/ipu.h
rename to drivers/video/imx/ipu.h
diff --git a/drivers/video/ipu_common.c b/drivers/video/imx/ipu_common.c
similarity index 100%
rename from drivers/video/ipu_common.c
rename to drivers/video/imx/ipu_common.c
diff --git a/drivers/video/ipu_disp.c b/drivers/video/imx/ipu_disp.c
similarity index 100%
rename from drivers/video/ipu_disp.c
rename to drivers/video/imx/ipu_disp.c
diff --git a/drivers/video/ipu_regs.h b/drivers/video/imx/ipu_regs.h
similarity index 100%
rename from drivers/video/ipu_regs.h
rename to drivers/video/imx/ipu_regs.h
diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c
similarity index 88%
rename from drivers/video/mxc_ipuv3_fb.c
rename to drivers/video/imx/mxc_ipuv3_fb.c
index 23cd55d..3e38d4b 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/imx/mxc_ipuv3_fb.c
@@ -17,13 +17,17 @@
 #include <linux/list.h>
 #include <linux/fb.h>
 #include <asm/io.h>
+#include <asm/mach-imx/video.h>
 #include <malloc.h>
 #include <video_fb.h>
-#include "videomodes.h"
+#include "../videomodes.h"
 #include "ipu.h"
 #include "mxcfb.h"
 #include "ipu_regs.h"
 
+#include <dm.h>
+#include <video.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static int mxcfb_map_video_memory(struct fb_info *fbi);
@@ -401,8 +405,14 @@
 				    fbi->fix.line_length;
 	}
 	fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);
+
+#if CONFIG_IS_ENABLED(DM_VIDEO)
+	fbi->screen_base = (char *)gd->video_bottom;
+#else
 	fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
 					    fbi->fix.smem_len);
+#endif
+
 	fbi->fix.smem_start = (unsigned long)fbi->screen_base;
 	if (fbi->screen_base == 0) {
 		puts("Unable to allocate framebuffer memory\n");
@@ -416,7 +426,9 @@
 
 	fbi->screen_size = fbi->fix.smem_len;
 
+#if CONFIG_IS_ENABLED(VIDEO)
 	gd->fb_base = fbi->fix.smem_start;
+#endif
 
 	/* Clear the screen */
 	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
@@ -611,3 +623,78 @@
 
 	return 0;
 }
+
+#if CONFIG_IS_ENABLED(DM_VIDEO)
+enum {
+	/* Maximum display size we support */
+	LCD_MAX_WIDTH		= 1920,
+	LCD_MAX_HEIGHT		= 1080,
+	LCD_MAX_LOG2_BPP	= VIDEO_BPP16,
+};
+
+static int ipuv3_video_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	u32 fb_start, fb_end;
+	int ret;
+
+	debug("%s() plat: base 0x%lx, size 0x%x\n",
+	      __func__, plat->base, plat->size);
+
+	ret = ipu_probe();
+	if (ret)
+		return ret;
+
+	ret = ipu_displays_init();
+	if (ret < 0)
+		return ret;
+
+	ret = mxcfb_probe(gpixfmt, gdisp, gmode);
+	if (ret < 0)
+		return ret;
+
+	uc_priv->xsize = gmode->xres;
+	uc_priv->ysize = gmode->yres;
+	uc_priv->bpix = LCD_MAX_LOG2_BPP;
+
+	/* Enable dcache for the frame buffer */
+	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+	fb_end = plat->base + plat->size;
+	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+					DCACHE_WRITEBACK);
+	video_set_flush_dcache(dev, true);
+
+	return 0;
+}
+
+struct ipuv3_video_priv {
+	ulong regs;
+};
+
+static int ipuv3_video_bind(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+
+	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
+		     (1 << LCD_MAX_LOG2_BPP) / 8;
+
+	return 0;
+}
+
+static const struct udevice_id ipuv3_video_ids[] = {
+	{ .compatible = "fsl,imx6q-ipu" },
+	{ }
+};
+
+U_BOOT_DRIVER(ipuv3_video) = {
+	.name	= "ipuv3_video",
+	.id	= UCLASS_VIDEO,
+	.of_match = ipuv3_video_ids,
+	.bind	= ipuv3_video_bind,
+	.probe	= ipuv3_video_probe,
+	.priv_auto_alloc_size = sizeof(struct ipuv3_video_priv),
+	.flags	= DM_FLAG_PRE_RELOC,
+};
+#endif /* CONFIG_DM_VIDEO */
diff --git a/drivers/video/mxcfb.h b/drivers/video/imx/mxcfb.h
similarity index 100%
rename from drivers/video/mxcfb.h
rename to drivers/video/imx/mxcfb.h
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index bd733f5..a587977 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -39,6 +39,12 @@
 	struct udevice *pwm;
 	uint channel;
 	uint period_ns;
+	/*
+	 * the polarity of one PWM
+	 * 0: normal polarity
+	 * 1: inverted polarity
+	 */
+	bool polarity;
 	u32 *levels;
 	int num_levels;
 	uint default_level;
@@ -57,7 +63,10 @@
 		(priv->max_level - priv->min_level + 1);
 	ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns,
 			     duty_cycle);
+	if (ret)
+		return log_ret(ret);
 
+	ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity);
 	return log_ret(ret);
 }
 
@@ -202,6 +211,8 @@
 		return log_msg_ret("Not enough arguments to pwm\n", -EINVAL);
 	priv->channel = args.args[0];
 	priv->period_ns = args.args[1];
+	if (args.args_count > 2)
+		priv->polarity = args.args[2];
 
 	index = dev_read_u32_default(dev, "default-brightness-level", 255);
 	cell = dev_read_prop(dev, "brightness-levels", &len);
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index 2ca19d4..c31303b 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -259,6 +259,43 @@
 	priv->escape = 0;
 
 	switch (ch) {
+	case 'A':
+	case 'B':
+	case 'C':
+	case 'D':
+	case 'E':
+	case 'F': {
+		int row, col, num;
+		char *s = priv->escape_buf;
+
+		/*
+		 * Cursor up/down: [%dA, [%dB, [%dE, [%dF
+		 * Cursor left/right: [%dD, [%dC
+		 */
+		s++;    /* [ */
+		s = parsenum(s, &num);
+		if (num == 0)			/* No digit in sequence ... */
+			num = 1;		/* ... means "move by 1". */
+
+		get_cursor_position(priv, &row, &col);
+		if (ch == 'A' || ch == 'F')
+			row -= num;
+		if (ch == 'C')
+			col += num;
+		if (ch == 'D')
+			col -= num;
+		if (ch == 'B' || ch == 'E')
+			row += num;
+		if (ch == 'E' || ch == 'F')
+			col = 0;
+		if (col < 0)
+			col = 0;
+		if (row < 0)
+			row = 0;
+		/* Right and bottom overflows are handled in the callee. */
+		set_cursor_position(priv, row, col);
+		break;
+	}
 	case 'H':
 	case 'f': {
 		int row, col;
@@ -309,6 +346,25 @@
 		}
 		break;
 	}
+	case 'K': {
+		struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+		int mode;
+
+		/*
+		 * Clear (parts of) current line
+		 *   [0K       - clear line to end
+		 *   [2K       - clear entire line
+		 */
+		parsenum(priv->escape_buf + 1, &mode);
+
+		if (mode == 2) {
+			int row, col;
+
+			get_cursor_position(priv, &row, &col);
+			vidconsole_set_row(dev, row, vid_priv->colour_bg);
+		}
+		break;
+	}
 	case 'm': {
 		struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
 		char *s = priv->escape_buf;
@@ -360,6 +416,13 @@
 				vid_priv->colour_fg = vid_console_color(
 						vid_priv, vid_priv->fg_col_idx);
 				break;
+			case 7:
+				/* reverse video */
+				vid_priv->colour_fg = vid_console_color(
+						vid_priv, vid_priv->bg_col_idx);
+				vid_priv->colour_bg = vid_console_color(
+						vid_priv, vid_priv->fg_col_idx);
+				break;
 			case 30 ... 37:
 				/* foreground color */
 				vid_priv->fg_col_idx &= ~7;
@@ -368,9 +431,11 @@
 						vid_priv, vid_priv->fg_col_idx);
 				break;
 			case 40 ... 47:
-				/* background color */
+				/* background color, also mask the bold bit */
+				vid_priv->bg_col_idx &= ~0xf;
+				vid_priv->bg_col_idx |= val - 40;
 				vid_priv->colour_bg = vid_console_color(
-							vid_priv, val - 40);
+						vid_priv, vid_priv->bg_col_idx);
 				break;
 			default:
 				/* ignore unsupported SGR parameter */
@@ -392,6 +457,32 @@
 	priv->escape = 0;
 }
 
+/* Put that actual character on the screen (using the CP437 code page). */
+static int vidconsole_output_glyph(struct udevice *dev, char ch)
+{
+	struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
+	int ret;
+
+	/*
+	 * Failure of this function normally indicates an unsupported
+	 * colour depth. Check this and return an error to help with
+	 * diagnosis.
+	 */
+	ret = vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ch);
+	if (ret == -EAGAIN) {
+		vidconsole_newline(dev);
+		ret = vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ch);
+	}
+	if (ret < 0)
+		return ret;
+	priv->xcur_frac += ret;
+	priv->last_ch = ch;
+	if (priv->xcur_frac >= priv->xsize_frac)
+		vidconsole_newline(dev);
+
+	return 0;
+}
+
 int vidconsole_put_char(struct udevice *dev, char ch)
 {
 	struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
@@ -429,23 +520,9 @@
 		priv->last_ch = 0;
 		break;
 	default:
-		/*
-		 * Failure of this function normally indicates an unsupported
-		 * colour depth. Check this and return an error to help with
-		 * diagnosis.
-		 */
-		ret = vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ch);
-		if (ret == -EAGAIN) {
-			vidconsole_newline(dev);
-			ret = vidconsole_putc_xy(dev, priv->xcur_frac,
-						 priv->ycur, ch);
-		}
+		ret = vidconsole_output_glyph(dev, ch);
 		if (ret < 0)
 			return ret;
-		priv->xcur_frac += ret;
-		priv->last_ch = ch;
-		if (priv->xcur_frac >= priv->xsize_frac)
-			vidconsole_newline(dev);
 		break;
 	}
 
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index f307cf2..14aac88 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -136,6 +136,7 @@
 		back = temp;
 	}
 	priv->fg_col_idx = fore;
+	priv->bg_col_idx = back;
 	priv->colour_fg = vid_console_color(priv, fore);
 	priv->colour_bg = vid_console_color(priv, back);
 }
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index 1cfeaa9..d761432 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -397,7 +397,7 @@
 	    EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 ||
 	    EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 ||
 	    EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 ||
-	    /* 3d formats are not supported*/
+	    /* 3d formats are not supported */
 	    EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0)
 		return -EINVAL;
 
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index e2c7060..57edeee 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -34,8 +34,6 @@
 
 #define CONFIG_MXC_UART
 
-#define CONFIG_MXC_OCOTP
-
 /* SATA Configs */
 #define CONFIG_SYS_SATA_MAX_DEVICE	1
 #define CONFIG_DWC_AHSATA_PORT_ID	0
@@ -217,7 +215,6 @@
 
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 0834ff5..7721907 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -240,7 +240,6 @@
  * add mass storage support and for gadget we add both RNDIS ethernet
  * and DFU.
  */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5a60806..37d058e 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -120,12 +120,6 @@
 #define CONFIG_ENV_OFFSET_REDUND       0x120000
 #endif
 
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_QSPI_SEL_GPIO                   48
-#define CONFIG_QSPI_QUAD_SUPPORT
-#define CONFIG_TI_EDMA3
-
 #ifndef CONFIG_SPL_BUILD
 #include <environment/ti/dfu.h>
 #include <environment/ti/mmc.h>
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 4899984..c14b010 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -92,11 +92,6 @@
 #define CONFIG_SYS_SPI_ARGS_SIZE        0x80000
 
 /* SPI SPL */
-#define CONFIG_TI_EDMA3
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
 
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_QSPI_QUAD_SUPPORT
-
 #endif /* __CONFIG_AM57XX_EVM_H */
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index ba4e96d..96169f5 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2013-2015 Toradex, Inc.
+ * Copyright 2013-2019 Toradex, Inc.
  *
  * Configuration settings for the Toradex Apalis iMX6
  */
@@ -34,17 +34,12 @@
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* I2C Configs */
-#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
-
-/* OCOTP Configs */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
 
 /* MMC Configs */
 #define CONFIG_FSL_USDHC
@@ -57,9 +52,6 @@
  * SATA Configs
  */
 #ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE	1
-#define CONFIG_DWC_AHSATA_PORT_ID	0
-#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
 #define CONFIG_LBA48
 #endif
 
@@ -82,11 +74,7 @@
 /* Client */
 #define CONFIG_USBD_HS
 
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
 /* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
@@ -115,37 +103,36 @@
 
 #define CONFIG_LOADADDR			0x12000000
 
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_DRIVE_SATA "sata "
-#else
-#define CONFIG_DRIVE_SATA
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
-#else
-#define CONFIG_DRIVE_MMC
-#endif
-
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+#else /* CONFIG_SPL_BUILD */
+#define BOOTENV
+#endif /* CONFIG_SPL_BUILD */
 
 #define DFU_ALT_EMMC_INFO \
 	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
 	"boot part 0 1;" \
 	"rootfs part 0 2;" \
-	"uImage fat 0 1;" \
-	"imx6q-colibri-eval-v3.dtb fat 0 1;" \
-	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
+	"zImage fat 0 1;" \
+	"imx6q-apalis-eval.dtb fat 0 1;" \
+	"imx6q-apalis-cam-eval.dtb fat 0 1"
 
 #define EMMC_BOOTCMD \
-	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"emmcboot=run setup; " \
 		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
 		"${vidargs}; echo Booting from internal eMMC chip...; "	\
 		"run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -155,7 +142,9 @@
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x11000000\0" \
-	"ramdisk_addr_r=0x12100000\0"
+	"pxefile_addr_r=0x17100000\0" \
+	"ramdisk_addr_r=0x12100000\0" \
+	"scriptaddr=0x17000000\0"
 
 #define NFS_BOOTCMD \
 	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
@@ -163,30 +152,30 @@
 		"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
 		"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
 		"run nfsdtbload; dhcp ${kernel_addr_r} " \
-		"&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
 		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
-#define SD_BOOTCMD						\
-	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+#define SD_BOOTCMD \
+	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"sdboot=run setup; " \
 		"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
 		"${vidargs}; echo Booting from SD card; " \
 		"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
 #define USB_BOOTCMD \
-	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
+	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
 		"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
 		"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -197,11 +186,12 @@
 #define FDT_FILE "imx6q-apalis_v1_0-eval.dtb"
 #endif
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
 	"bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
-		"run nfsboot ; echo ; echo nfsboot failed ; " \
-		"usb start ;" \
+		"run distro_bootcmd ; " \
+		"usb start ; " \
 		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
-	"boot_file=uImage\0" \
+	"boot_file=zImage\0" \
 	"console=ttymxc0\0" \
 	"defargs=enable_wait_mode=off vmalloc=400M\0" \
 	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
@@ -214,8 +204,10 @@
 	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
 		"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
 		"flash_eth.img && source ${loadaddr}\0" \
-	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
-		"${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \
+		"|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \
+		" ${loadaddr} flash_blk.img && " \
 		"source ${loadaddr}\0" \
 	"setup=setenv setupargs fec_mac=${ethaddr} " \
 		"consoleblank=0 no_console_suspend=1 console=tty1 " \
@@ -255,7 +247,6 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* environment organization */
-
 #define CONFIG_ENV_SIZE			(8 * 1024)
 
 #if defined(CONFIG_ENV_IS_IN_MMC)
@@ -266,8 +257,6 @@
 #define CONFIG_SYS_MMC_ENV_PART		1
 #endif
 
-#define CONFIG_OF_SYSTEM_SETUP
-
 #define CONFIG_CMD_TIME
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index 4f28f52..a248146 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -187,7 +187,6 @@
 /* UBI support */
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 /* check this console not needed, after test remove it */
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index ccbdc0a..98ec0d6 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -251,7 +251,6 @@
  * add mass storage support and for gadget we add both RNDIS ethernet
  * and DFU.
  */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
 #define CONFIG_AM335X_USB1
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index fb9c2a6..3d4d08a 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -387,7 +387,6 @@
  * add mass storage support and for gadget we add both RNDIS ethernet
  * and DFU.
  */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index a012705..05ebb7d 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -1,24 +1,271 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
  * Copyright 2016 3ADEV <http://3adev.com>
  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
  *
- * Configuration settings for the phytec PCM-052 SoM-based BK4R1.
+ * Configuration settings for BK4R1.
  */
 
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
 /* Define the BK4r1-specific env commands */
-#define PCM052_EXTRA_ENV_SETTINGS \
+#define BK4_EXTRA_ENV_SETTINGS \
+	"bootlimit=3\0" \
+	"eraseuserdata=false\0" \
+	"altbootcmd=led 5 on; " \
+		"boot\0" \
 	"set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
-	"set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"
+	"set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \
+	"set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\
+	"set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"\
+	"set_gpio6=mw 0x40048018 0x282; mw 0x400ff008 0x40\0"\
+	"manage_userdata=" MANAGE_USERDATA "\0"\
+	"ncenable=true\0"\
+	"ncserverip=192.168.0.77\0"\
+	"if_netconsole=ping $ncserverip\0"\
+	"start_netconsole=setenv ncip $serverip; setenv bootdelay 10;" \
+	     "setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \
+	"preboot=" BK4_NET_INIT \
+		"if ${ncenable}; then run if_netconsole start_netconsole; fi\0"
 
 /* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/
-#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; "
+#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \
+			"run manage_userdata; "
+
+/* Enable PREBOOT variable */
+#define CONFIG_PREBOOT
+
+/* Set ARP_TIMEOUT to 500ms */
+#define CONFIG_ARP_TIMEOUT 500UL
+
+/* Set ARP_TIMEOUT_COUNT to 3 repetitions */
+#define CONFIG_NET_RETRY_COUNT	5
 
 /* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */
-#define PCM052_NET_INIT "run set_gpio122; "
+#define BK4_NET_INIT "run set_gpio122;"
 
-/* add NOR to MTD env */
+/* Check if userdata volume shall be erased */
+#define MANAGE_USERDATA "if ${eraseuserdata}; " \
+						"then ubi part system; " \
+						"ubi remove userdata; " \
+						"ubi create userdata; " \
+						"ubi detach; " \
+						"setenv eraseuserdata false; " \
+						"saveenv; " \
+						"fi; "
 
-/* now include standard PCM052 config */
+/* Autoboot options */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Enter passphrase to stop autoboot, booting in %d seconds\n"
+#define CONFIG_AUTOBOOT_STOP_STR "123"
 
-#include "configs/pcm052.h"
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 4 * SZ_1M)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define IMX_FEC1_BASE			ENET1_BASE_ADDR
+
+/* QSPI Configs*/
+#ifdef CONFIG_FSL_QSPI
+#define FSL_QSPI_FLASH_SIZE		(SZ_16M)
+#define FSL_QSPI_FLASH_NUM		2
+#define CONFIG_SYS_FSL_QSPI_LE
+#endif
+
+#define CONFIG_LOADADDR	0x82000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_BOARD_SIZE_LIMIT		520192
+
+/* boot command, including the target-defined one if any */
+#define CONFIG_BOOTCOMMAND	BK4_BOOTCOMMAND "run bootcmd_nand"
+
+/* Extra env settings (including the target-defined ones if any) */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BK4_EXTRA_ENV_SETTINGS \
+	"autoload=no\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"blimg_file=u-boot.vyb\0" \
+	"blimg_addr=0x81000000\0" \
+	"dtbkernel_file=fitImage\0" \
+	"dtbkernel_addr=0x82000000\0" \
+	"ram_file=uRamdisk\0" \
+	"ram_addr=0x83000000\0" \
+	"filesys=rootfs.ubifs\0" \
+	"sys_addr=0x81000000\0" \
+	"nfs_root=/path/to/nfs/root\0" \
+	"tftptimeout=1000\0" \
+	"tftptimeoutcountmax=1000000\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"ipaddr=192.168.0.60\0" \
+	"serverip=192.168.0.1\0" \
+	"bootargs_base=setenv bootargs rw " \
+	"console=ttyLP1,115200n8\0" \
+	"bootargs_sd=setenv bootargs ${bootargs} " \
+		"root=/dev/mmcblk0p2 rootwait\0" \
+	"bootargs_nand=setenv bootargs ${bootargs} " \
+		"ubi.mtd=5 rootfstype=" \
+				"ubifs root=ubi0:rootfs${active_workset}\0" \
+	"bootargs_ram=setenv bootargs ${bootargs} " \
+		"root=/dev/ram rw initrd=${ram_addr}\0" \
+	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
+		"fatload mmc 0:2 ${dtbkernel_addr} ${dtbkernel_file}; " \
+		"bootm ${dtbkernel_addr}\0" \
+	"bootcmd_nand=sf probe;run bootargs_base bootargs_nand bootargs_mtd; " \
+		"ubi part dtbkernel; " \
+		"ubi readvol ${dtbkernel_addr} dtbkernel${active_workset}; " \
+		"led 0 on; " \
+		"bootm ${dtbkernel_addr}\0" \
+	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
+		"nand read ${fdt_addr} dtb; " \
+		"nand read ${kernel_addr} kernel; " \
+		"nand read ${ram_addr} root; " \
+		"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
+	"update_bootloader_from_sd=if fatload mmc 0:2 ${blimg_addr} " \
+		"${blimg_file}; " \
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part bootloader; " \
+		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
+	"update_bootloader_from_tftp=if tftp ${blimg_addr} "\
+		"${tftpdir}${blimg_file}; "\
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part bootloader; " \
+		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
+	"update_dtbkernel_from_sd=if fatload mmc 0:2 ${dtbkernel_addr} " \
+		"${dtbkernel_file}; " \
+		"then sf probe; " \
+		"ubi part dtbkernel; " \
+		"ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \
+		"${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_dtbkernel_from_tftp=if tftp ${dtbkernel_addr} " \
+		"${tftpdir}${dtbkernel_file}; " \
+		"then sf probe; " \
+		"ubi part dtbkernel; " \
+		"ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \
+		"${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_ramdisk_from_sd=if fatload mmc 0:2 ${ram_addr} " \
+		"${ram_file}; " \
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part initrd; " \
+		"nand write ${ram_addr} initrd ${filesize}; fi\0" \
+	"update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
+		"then sf probe; " \
+		"nand erase.part initrd; " \
+		"nand write ${ram_addr} initrd ${filesize}; fi\0" \
+	"update_rootfs_from_sd=if fatload mmc 0:2 ${sys_addr} " \
+		"${filesys}; " \
+		"then sf probe; " \
+		"ubi part system; " \
+		"ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
+		"then sf probe; " \
+		"ubi part system; " \
+		"ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \
+		"ubi detach; fi\0" \
+	"setup_dtbkernel=nand erase.part dtbkernel; " \
+		"ubi part dtbkernel; " \
+		"ubi create dtbkernel1 972000 s; " \
+		"ubi create dtbkernel2 972000 s; " \
+		"ubi detach\0" \
+	"setup_system=nand erase.part system; " \
+		"ubi part system; " \
+		"ubi create rootfs1 15E15000 d; " \
+		"ubi create rootfs2 15E15000 d; " \
+		"ubi create userdata; " \
+		"ubi detach\0" \
+	"setup_nor1=" BK4_NET_INIT \
+		"if tftp ${sys_addr} ${tftpdir}ubinor1.img; " \
+		"then sf probe 0:0; " \
+		"sf erase 0 01000000; " \
+		"mtdparts default; " \
+		"ubi part nor; " \
+		"ubi create nor1fs; " \
+		"ubi write ${sys_addr} nor1fs ${filesize}; " \
+		"ubi detach; fi\0" \
+	"setup_nor2=" BK4_NET_INIT \
+		"if tftp ${sys_addr} ${tftpdir}ubinor2.img; " \
+		"then sf probe 0:1; " \
+		"sf erase 0 01000000; " \
+		"mtdparts default; " \
+		"ubi part nor; " \
+		"ubi create nor2fs; " \
+		"ubi write ${sys_addr} nor2fs ${filesize}; " \
+		"ubi detach; fi\0" \
+	"prepare_install_bk4r1_envs=" \
+		"echo 'Preparing envs for SD card recovery!';" \
+		"setenv ipaddr 192.168.0.99;" \
+		"setenv serverip 192.168.0.50;" \
+		"\0" \
+	"install_bk4r1rs="\
+		"led 0 on; " \
+		"nand erase.chip; mtdparts default; "\
+		"led 1 on; "\
+		"run setup_dtbkernel; " \
+		"run setup_system; " \
+		"led 2 on;" \
+		"run update_bootloader_from_sd; "\
+		"run update_dtbkernel_from_sd; "\
+		"run update_rootfs_from_sd; "\
+		"setenv bootcmd 'run bootcmd_nand'; "\
+		"saveenv; " \
+		"led 3 on; " \
+		"echo Finished - Please Power off, REMOVE SDCARD and set boot" \
+			"source to NAND\0" \
+	"active_workset=1\0"
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical memory map */
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE		(SZ_512M)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE	(SZ_128K)
+#define CONFIG_ENV_SIZE		(SZ_8K)
+#define CONFIG_ENV_OFFSET	0x200000
+#define CONFIG_ENV_SIZE_REDUND	(SZ_8K)
+#define CONFIG_ENV_OFFSET_REDUND	0x220000
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
index ae9b75b..84c801d 100644
--- a/include/configs/brppt1.h
+++ b/include/configs/brppt1.h
@@ -182,9 +182,6 @@
 #define CONFIG_NAND_OMAP_GPMC_WSCFG	1
 #endif /* CONFIG_NAND */
 
-/* USB configuration */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-
 #if defined(CONFIG_SPI)
 /* SPI Flash */
 #define CONFIG_SYS_SPI_U_BOOT_OFFS		0x40000
diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h
index 601b30d..7309e7d 100644
--- a/include/configs/brxre1.h
+++ b/include/configs/brxre1.h
@@ -68,9 +68,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-/* USB configuration */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-
 /* Environment */
 #define CONFIG_SYS_MMC_ENV_DEV		1
 #define CONFIG_SYS_MMC_ENV_PART		2
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index ad0a64a..07c6409 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -60,7 +60,6 @@
 #define CONFIG_USBD_HS
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index 4372280..db990fc 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -148,7 +148,6 @@
 
 /* USB configuration */
 #define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_AM335X_USB1
 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
 
diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h
deleted file mode 100644
index bf2bb44..0000000
--- a/include/configs/cl-som-am57x.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration settings for CompuLab CL-SOM-AM57x board
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- */
-
-#ifndef __CONFIG_CL_SOM_AM57X_H
-#define __CONFIG_CL_SOM_AM57X_H
-
-#define CONSOLEDEV			"ttyO2"
-#define CONFIG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
-
-#define CONFIG_SYS_OMAP_ABE_SYSCK
-
-#define PARTS_DEFAULT
-
-#include <configs/ti_omap5_common.h>
-
-/* misc */
-#define CONFIG_REVISION_TAG
-
-/* PMIC I2C bus number */
-#define CONFIG_SYS_SPD_BUS_NUM 3
-
-/* SPI Flash support */
-#define CONFIG_TI_SPI_MMAP
-
-/* SPI SPL defines */
-/* Offsets: 0K - SPL1, 64K - SPL2, 128K - SPL3, 192K - SPL4, 256K - U-Boot */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS	(256 * 1024)
-#define CONFIG_SPL_SPI_SUPPORT
-
-/* SD/MMC RAW/FS boot */
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-
-/* Environment */
-#define CONFIG_ENV_SIZE			(16 << 10) /* 16 KiB env size */
-
-#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
-#define CONFIG_ENV_OFFSET		(768 * 1024)
-
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
-#define CONFIG_SYS_I2C_EEPROM_BUS       3
-
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_EEPROM_SIZE		256
-
-#ifndef CONFIG_SPL_BUILD
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
-#define CONFIG_SYS_SCSI_MAX_LUN		1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-						CONFIG_SYS_SCSI_MAX_LUN)
-/* PCA9555 GPIO expander support */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR     0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x20, 16} }
-
-#endif /* !CONFIG_SPL_BUILD */
-
-/* USB xHCI HOST */
-#define CONFIG_USB_XHCI_OMAP
-
-#define CONFIG_OMAP_USB3PHY1_HOST
-
-/* USB Networking options */
-
-/* CPSW Ethernet */
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_PHY_ATHEROS
-#define CONFIG_SYS_RX_ETH_BUFFER	64
-#define PHY_ANEG_TIMEOUT		8000
-
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_NET_RETRY_COUNT		10
-
-/* Default environment */
-#undef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	DEFAULT_LINUX_BOOT_ENV \
-	"autoload=no\0" \
-	"baudrate=115200\0" \
-	"console=ttyO2,115200n8\0" \
-	"bootdelay=3\0" \
-	"fdtfile=am57xx-sbc-am57x.dtb\0" \
-	"kernel=zImage-cl-som-am57x\0" \
-	"bootscr=bootscr.img\0" \
-	"displaytype=hdmi\0" \
-	"bootkernel=bootz ${loadaddr} - ${fdtaddr}\0" \
-	"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
-	"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
-	"emmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
-	"emmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
-	"load_mmc=mmc dev ${mmcdev} && mmc rescan && " \
-		"run mmcloadkernel && run mmcloadfdt\0" \
-	"mmcroot=/dev/mmcblk1p2\0" \
-	"mmcrootfstype=ext4 rw rootwait\0" \
-	"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"mmcbootscript=setenv mmcdev 0; mmc dev ${mmcdev} && mmc rescan && " \
-		"load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \
-		"echo Running bootscript from MMC/SD Card ... && " \
-		"source ${loadaddr}\0" \
-	"mmcboot=setenv mmcdev 0 && run load_mmc && " \
-		"run mmcargs && echo Booting from MMC/SD Card ... && " \
-		"run bootkernel\0" \
-	"emmcroot=/dev/mmcblk0p2\0" \
-	"emmcrootfstype=ext4 rw rootwait\0" \
-	"emmcargs=setenv bootargs console=${console} " \
-		"root=${emmcroot} " \
-		"rootfstype=${emmcrootfstype}\0" \
-	"emmcbootscript=setenv mmcdev 1; mmc dev ${mmcdev} && mmc rescan && " \
-		"load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \
-		"echo Running bootscript from eMMC ... && " \
-		"source ${loadaddr}\0" \
-	"emmcboot=setenv mmcdev 1 && run load_mmc && " \
-		"run emmcargs && echo Booting from eMMC ... && " \
-		"run bootkernel\0" \
-	"sataroot=/dev/sda2\0" \
-	"satarootfstype=ext4 rw rootwait\0" \
-	"load_sata=load scsi 0 ${loadaddr} ${kernel} && " \
-		"load scsi 0 ${fdtaddr} ${fdtfile}\0" \
-	"sataargs=setenv bootargs console=${console} " \
-		"root=${sataroot} " \
-		"rootfstype=${satarootfstype}\0" \
-	"satabootscript=load scsi 0 ${loadaddr} ${bootscr} && " \
-		"echo Running bootscript from SATA ... && " \
-		"source ${loadaddr}\0" \
-	"sataboot=run load_sata && run sataargs && " \
-		"echo Booting from SATA ... && " \
-		"run bootkernel\0"
-
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
-	"run mmcbootscript || run mmcboot || " \
-	"run satabootscript || run sataboot || " \
-	"run emmcbootscript || run emmcboot"
-
-
-#endif /* __CONFIG_CL_SOM_AM57X_H */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index dfd96ff..2e8dda8 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -212,7 +212,6 @@
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
 
 /* Display */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_IMX_HDMI
 
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index ffe4a44..e4e37e5 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -53,9 +53,6 @@
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_AM437X_USB2PHY2_HOST
 
-/* SPI Flash support */
-#define CONFIG_TI_SPI_MMAP
-
 /* Power */
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 2d40ceb..803c9be 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2013-2015 Toradex, Inc.
+ * Copyright 2013-2019 Toradex, Inc.
  *
  * Configuration settings for the Toradex Colibri iMX6
  */
@@ -32,17 +32,12 @@
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* I2C Configs */
-#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
-
-/* OCOTP Configs */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
 
 /* MMC Configs */
 #define CONFIG_FSL_USDHC
@@ -70,11 +65,7 @@
 /* Client */
 #define CONFIG_USBD_HS
 
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
 /* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
@@ -103,31 +94,35 @@
 
 #define CONFIG_LOADADDR			0x12000000
 
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
-#else
-#define CONFIG_DRIVE_MMC
-#endif
-
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+#else /* CONFIG_SPL_BUILD */
+#define BOOTENV
+#endif /* CONFIG_SPL_BUILD */
 
 #define DFU_ALT_EMMC_INFO \
 	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
 	"boot part 0 1;" \
 	"rootfs part 0 2;" \
-	"uImage fat 0 1;" \
-	"imx6q-colibri-eval-v3.dtb fat 0 1;" \
-	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
+	"zImage fat 0 1;" \
+	"imx6dl-colibri-eval-v3.dtb fat 0 1;" \
+	"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
 
 #define EMMC_BOOTCMD \
-	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"emmcboot=run setup; " \
 		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
 		"${vidargs}; echo Booting from internal eMMC chip...; "	\
 		"run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
@@ -137,7 +132,9 @@
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"kernel_addr_r=0x11000000\0" \
-	"ramdisk_addr_r=0x12100000\0"
+	"pxefile_addr_r=0x17100000\0" \
+	"ramdisk_addr_r=0x12100000\0" \
+	"scriptaddr=0x17000000\0"
 
 #define NFS_BOOTCMD \
 	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
@@ -145,40 +142,41 @@
 		"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
 		"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
 		"run nfsdtbload; dhcp ${kernel_addr_r} " \
-		"&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
 		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
-#define SD_BOOTCMD						\
-	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+#define SD_BOOTCMD \
+	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"sdboot=run setup; " \
 		"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
 		"${vidargs}; echo Booting from SD card; " \
 		"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
 #define USB_BOOTCMD \
-	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
+	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
 		"rootwait\0" \
 	"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
 		"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
 		"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
 		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
 	"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
 		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
 
 #define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
 	"bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
-		"run nfsboot ; echo ; echo nfsboot failed ; " \
-		"usb start ;" \
+		"run distro_bootcmd ; " \
+		"usb start ; " \
 		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
-	"boot_file=uImage\0" \
+	"boot_file=zImage\0" \
 	"console=ttymxc0\0" \
 	"defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
 	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
@@ -240,8 +238,6 @@
 #define CONFIG_SYS_MMC_ENV_PART		1
 #endif
 
-#define CONFIG_OF_SYSTEM_SETUP
-
 #define CONFIG_CMD_TIME
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 31ff8a0..0d57e30 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2015-2016 Toradex, Inc.
+ * Copyright 2015-2019 Toradex, Inc.
  *
  * Configuration settings for the Toradex VF50/VF61 modules.
  *
@@ -12,15 +12,12 @@
 #define __CONFIG_H
 
 #include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
 
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_VIDEO_LOGO
@@ -32,7 +29,7 @@
 #endif
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * SZ_1M)
 
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -40,17 +37,6 @@
 /* NAND support */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
-
-/* Dynamic MTD partition support */
-
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	1
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET1_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RMII
-#define CONFIG_FEC_MXC_PHYADDR          0
 
 #define CONFIG_IPADDR		192.168.10.2
 #define CONFIG_NETMASK		255.255.255.0
@@ -62,13 +48,15 @@
 /* We boot from the gfxRAM area of the OCRAM. */
 #define CONFIG_BOARD_SIZE_LIMIT		520192
 
-#define SD_BOOTCMD \
-	"sdargs=root=/dev/mmcblk0p2 rw rootwait\0"	\
-	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
-	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
-	"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
-	"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
-	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"pxefile_addr_r=0x87100000\0" \
+	"ramdisk_addr_r=0x82100000\0" \
+	"scriptaddr=0x87000000\0"
 
 #define NFS_BOOTCMD \
 	"nfsargs=ip=:::::eth0: root=/dev/nfs\0"	\
@@ -79,7 +67,15 @@
 	"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
 	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
-#define UBI_BOOTCMD	\
+#define SD_BOOTCMD \
+	"sdargs=root=/dev/mmcblk0p2 ro rootwait\0"	\
+	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
+	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
+	"load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
+	"load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
+	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define UBI_BOOTCMD \
 	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
 	"ubi.fm_autoconvert=1\0" \
 	"ubiboot=run setup; " \
@@ -90,36 +86,43 @@
 	"ubi read ${fdt_addr_r} dtb && " \
 	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
-#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
+#define CONFIG_BOOTCOMMAND "run ubiboot; " \
+	"setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
 
 #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"kernel_addr_r=0x82000000\0" \
-	"fdt_addr_r=0x84000000\0" \
-	"kernel_file=zImage\0" \
-	"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	SD_BOOTCMD \
+	UBI_BOOTCMD \
+	"console=ttyLP0\0" \
+	"defargs=user_debug=30\0" \
+	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
 	"fdt_board=eval-v3\0" \
 	"fdt_fixup=;\0" \
-	"defargs=\0" \
-	"console=ttyLP0\0" \
-	"setup=setenv setupargs " \
-	"console=tty1 console=${console}" \
-	",${baudrate}n8 ${memargs}\0" \
-	"setsdupdate=mmc rescan && set interface mmc && " \
-	"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
-	"source ${loadaddr}\0" \
-	"setusbupdate=usb start && set interface usb && " \
-	"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
-	"source ${loadaddr}\0" \
-	"setupdate=run setsdupdate || run setusbupdate\0" \
+	"kernel_file=zImage\0" \
 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
-	"video-mode=dcufb:640x480-16@60,monitor=lcd\0" \
+	"setsdupdate=mmc rescan && set interface mmc && " \
+		"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"setup=setenv setupargs console=tty1 console=${console}" \
+		",${baudrate}n8 ${memargs}\0" \
+	"setupdate=run setsdupdate || run setusbupdate\0" \
+	"setusbupdate=usb start && set interface usb && " \
+		"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
 	"splashpos=m,m\0" \
-	SD_BOOTCMD \
-	NFS_BOOTCMD \
-	UBI_BOOTCMD
+	"video-mode=dcufb:640x480-16@60,monitor=lcd\0"
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
@@ -133,7 +136,7 @@
 
 /* Physical memory map */
 #define PHYS_SDRAM			(0x80000000)
-#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE			(256 * SZ_1M)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
@@ -145,13 +148,6 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* Environment organization */
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
-#define CONFIG_ENV_SIZE			(8 * 1024)
-#endif
-
 #ifdef CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			(64 * 2048)
 #define CONFIG_ENV_RANGE		(4 * 64 * 2048)
@@ -159,13 +155,10 @@
 #endif
 
 /* USB Host Support */
-#define CONFIG_USB_EHCI_VF
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 
 /* USB DFU */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
-
-/* USB Storage */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 48514ff..3eee382 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -48,11 +48,6 @@
 #define CONFIG_FEC_MXC_PHYADDR		0
 #define CONFIG_ARP_TIMEOUT		200UL
 
-/* Fuses */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 7441f4a..f6be659 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -72,10 +72,6 @@
 #define CONFIG_NET_RETRY_COUNT		10
 #define CONFIG_PHY_TI
 
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_QSPI_QUAD_SUPPORT
-
 /*
  * Default to using SPI for environment, etc.
  * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
@@ -98,7 +94,6 @@
 #endif
 
 /* SPI SPL */
-#define CONFIG_TI_EDMA3
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
 
 #define CONFIG_SUPPORT_EMMC_BOOT
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 5142680..858bed0 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -86,7 +86,6 @@
 #endif
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 3336578..196f114 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -35,8 +35,6 @@
 
 #define CONFIG_MXC_UART
 
-#define CONFIG_MXC_OCOTP
-
 /* SATA Configs */
 #ifdef CONFIG_CMD_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	1
@@ -45,10 +43,6 @@
 #define CONFIG_LBA48
 #endif
 
-/* MMC Configs */
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
-
 /* USB Configs */
 #ifdef CONFIG_USB
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
@@ -77,12 +71,37 @@
 
 #define CONFIG_LOADADDR	0x12000000
 
+#ifdef CONFIG_NFS_CMD
+#define NETWORKBOOT \
+        "setnetworkboot=" \
+                "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \
+                "setenv gatewayip 172.16.2.20; setenv nfsserver 172.16.2.20; " \
+                "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \
+                "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \
+                "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \
+                "setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \
+                "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \
+                "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \
+        "networkboot=" \
+                "run setnetworkboot; " \
+                "nfs ${loadaddr} /srv/nfs/fitImage; " \
+                "bootm ${loadaddr}#conf@${confidx}\0" \
+
+#define CONFIG_NETWORKBOOTCOMMAND \
+	"run networkboot; " \
+
+#else
+#define NETWORKBOOT \
+
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	NETWORKBOOT \
 	"bootcause=POR\0" \
 	"image=/boot/fitImage\0" \
 	"fdt_high=0xffffffff\0" \
 	"dev=mmc\0" \
-	"devnum=1\0" \
+	"devnum=2\0" \
 	"rootdev=mmcblk0p\0" \
 	"quiet=quiet loglevel=0\0" \
 	"console=" CONSOLE_DEV "\0" \
@@ -140,13 +159,14 @@
 #define CONFIG_USBBOOTCOMMAND \
 	"echo Unsupported; " \
 
-#ifdef CONFIG_CMD_USB
+#ifdef CONFIG_NFS_CMD
+#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND
+#elif CONFIG_CMD_USB
 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
 #else
 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
 #endif
 
-#define CONFIG_ARP_TIMEOUT     200UL
 
 /* Miscellaneous configurable options */
 
@@ -176,18 +196,10 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	3
 
 /* Framebuffer */
-#define CONFIG_VIDEO
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_FG_COL 0xFF
-#define CONFIG_SYS_CONSOLE_BG_COL 0x00
 #define CONFIG_HIDE_LOGO_VERSION
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #define CONFIG_CMD_BMP
-#endif
 
 #define CONFIG_PWM_IMX
 #define CONFIG_IMX6_PWM_PER_CLK	66000000
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 84ee44e..93608e5 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -132,7 +132,6 @@
 #define CONFIG_NETCONSOLE
 
 /* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index a9e38a7..6094d1b 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -230,7 +230,6 @@
 
 #define CONFIG_MXC_GPIO
 
-#define CONFIG_MXC_OCOTP
 #define CONFIG_CMD_FUSE
 
 /* I2C Configs */
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index b6b27ee..d2ebf92 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -31,11 +31,6 @@
 #define CONFIG_FEC_MXC_PHYADDR		0
 #define CONFIG_ARP_TIMEOUT		200UL
 
-/* Fuses */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 51456fb..84d0613 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -138,7 +138,6 @@
  * LCD
  */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index eb172c9..9bf9773 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -68,7 +68,6 @@
 
 /* Framebuffer and LCD */
 #define CONFIG_PREBOOT
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index 3ed5ee3..1e3ea88 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -161,7 +161,6 @@
 
 /* Framebuffer and LCD */
 #define CONFIG_PREBOOT
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 816164e..2d18f05 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -178,7 +178,6 @@
 
 /* Framebuffer and LCD */
 #define CONFIG_PREBOOT
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index d2a8e65..f002324 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -30,10 +30,6 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	2
-
 /* Eth Configs */
 
 #define CONFIG_FEC_MXC
@@ -89,10 +85,10 @@
 	"nfsroot=/opt/springdale/rd\0" \
 	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
 		"${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
-	"choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \
-		"set getcmd dhcp; else set kern_ipconf " \
+	"choose_ip=if test $use_dhcp = 1; then setenv kern_ipconf ip=dhcp; " \
+		"setenv getcmd dhcp; else setenv kern_ipconf " \
 		"ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \
-		"set getcmd tftp; fi\0" \
+		"setenv getcmd tftp; fi\0" \
 	"nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \
 		"${nfsserver}:${image}; bootm ${loadaddr}\0" \
 
@@ -101,7 +97,7 @@
 	"image=/boot/fitImage\0" \
 	"fdt_high=0xffffffff\0" \
 	"dev=mmc\0" \
-	"devnum=0\0" \
+	"devnum=2\0" \
 	"rootdev=mmcblk0p\0" \
 	"quiet=quiet loglevel=0\0" \
 	"console=" CONSOLE_DEV "\0" \
@@ -219,9 +215,4 @@
 #define CONFIG_PWM_IMX
 #define CONFIG_IMX6_PWM_PER_CLK 66666000
 
-/* Framebuffer and LCD */
-#ifdef CONFIG_VIDEO
-	#define CONFIG_VIDEO_IPUV3
-#endif
-
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index cdc8833..6b20c6d 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -57,9 +57,6 @@
 /* MMC */
 #define CONFIG_FSL_USDHC
 
-/* Fuses */
-#define CONFIG_MXC_OCOTP
-
 /* Secure boot (HAB) support */
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CSF_SIZE			0x2000
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index a62e14f..7b4ae21 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -35,7 +35,6 @@
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 6fe0467..c137612 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -185,7 +185,6 @@
 #endif
 
 /* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index a895c93..cc7e872 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -42,9 +42,6 @@
 /* MMC */
 #define CONFIG_FSL_USDHC
 
-/* Fuses */
-#define CONFIG_MXC_OCOTP
-
 #define CONFIG_ARMV7_SECURE_BASE	0x00900000
 
 #define CONFIG_ARMV7_PSCI_1_0
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index d941caa..afaa908 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -58,7 +58,6 @@
 #define CONFIG_MXC_USB_FLAGS	0
 
 /* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 25736f3..bb5bf80 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -125,7 +125,6 @@
 
 /* Video output */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index e125a38..fb8f3c8 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -9,6 +9,7 @@
 #define __CONFIG_H
 
 #include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -16,7 +17,7 @@
 #define CONFIG_CMDLINE_TAG
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * SZ_1M)
 
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -24,48 +25,14 @@
 /* NAND support */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 
-#ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
-
-#define CONFIG_JFFS2_NAND
-
-/* Dynamic MTD partition support */
-
-#endif
-
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	1
-
-/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RMII
-#define CONFIG_FEC_MXC_PHYADDR          0
-
 /* QSPI Configs*/
-
 #ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_SIZE		(SZ_16M)
 #define FSL_QSPI_FLASH_NUM		2
 #define CONFIG_SYS_FSL_QSPI_LE
 #endif
 
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC_I2C3
-#define CONFIG_SYS_I2C_MXC
-
-/* RTC (actually an RV-4162 but M41T62-compatible) */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_RTC_BUS_NUM 2
-
-/* EEPROM (24FC256) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_BUS 2
-
 
 #define CONFIG_LOADADDR			0x82000000
 
@@ -188,7 +155,7 @@
 
 /* Physical memory map */
 #define PHYS_SDRAM			(0x80000000)
-#define PHYS_SDRAM_SIZE			(CONFIG_PCM052_DDR_SIZE * 1024 * 1024)
+#define PHYS_SDRAM_SIZE			(CONFIG_PCM052_DDR_SIZE * SZ_1M)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
@@ -201,17 +168,17 @@
 
 /* environment organization */
 #ifdef CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SIZE			(SZ_8K)
 
-#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #endif
 
 #ifdef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
-#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(SZ_128K)
+#define CONFIG_ENV_SIZE			(SZ_8K)
 #define CONFIG_ENV_OFFSET		0xA0000
-#define CONFIG_ENV_SIZE_REDUND		(8 * 1024)
+#define CONFIG_ENV_SIZE_REDUND		(SZ_8K)
 #define CONFIG_ENV_OFFSET_REDUND	0xC0000
 #endif
 
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 48f1f7b..a535d0c 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -157,7 +157,6 @@
  * board schematic and physical port wired to each.  Then for host we
  * add mass storage support.
  */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index f44a428..1170f24 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -150,8 +150,6 @@
 /*
  * USB configuration
  */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 09c9b7c..f9e2cdc 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -338,6 +338,7 @@
 	"scriptaddr=0x02100000\0" \
 	"pxefile_addr_r=0x02200000\0" \
 	"ramdisk_addr_r=0x02300000\0" \
+	"socfpga_legacy_reset_compat=1\0" \
 	BOOTENV
 
 #endif
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b01d1c3..a498393 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -104,13 +104,7 @@
 #define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
 
 #ifdef CONFIG_AHCI
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SUNXI_AHCI
 #define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
-#define CONFIG_SYS_SCSI_MAX_LUN		1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-					 CONFIG_SYS_SCSI_MAX_LUN)
 #endif
 
 #define CONFIG_SETUP_MEMORY_TAGS
@@ -449,7 +443,6 @@
 	"stdout=serial,vga\0" \
 	"stderr=serial,vga\0"
 #elif CONFIG_DM_VIDEO
-#define CONFIG_SYS_WHITE_ON_BLACK
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial,vidconsole\0" \
 	"stderr=serial,vidconsole\0"
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index b06c909..a753d41 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -40,13 +40,6 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE /* select UART1/UART2 */
 
-/* Filesystems / image support */
-
-/* MMC */
-#define CONFIG_SYS_FSL_USDHC_NUM	3
-#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
-
 /* Ethernet */
 #define CONFIG_FEC_MXC
 #define CONFIG_FEC_MXC
@@ -58,7 +51,6 @@
 
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
@@ -77,11 +69,11 @@
 #define CONFIG_DWC_AHSATA_PORT_ID	0
 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
 #define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
 #endif
 
 /* USB */
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #ifdef CONFIG_CMD_USB_MASS_STORAGE
@@ -98,23 +90,6 @@
 #endif /* CONFIG_USB_KEYBOARD */
 #endif /* CONFIG_CMD_USB      */
 
-/* RTC */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1307
-#define CONFIG_SYS_RTC_BUS_NUM		2
-#endif
-
-/* I2C */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_I2C_EDID
-#endif
-
 /* Environment organization */
 #define CONFIG_SYS_MMC_ENV_DEV		2 /* overwritten on SD boot */
 #define CONFIG_SYS_MMC_ENV_PART		1 /* overwritten on SD boot */
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 686a383..ba85bc9 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -19,10 +19,6 @@
 /* Enable passing of ATAGs */
 #define CONFIG_CMDLINE_TAG
 
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index b03a1c5..2e6262f 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -32,26 +32,11 @@
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
 
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED		100000
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
-
 /* MMC Configuration */
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
 /* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS		0
 
@@ -64,8 +49,6 @@
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
@@ -74,7 +57,6 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
-#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"console=ttymxc0\0" \
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 27a8e4d..91ae708 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -108,15 +108,6 @@
 # define PHY_ANEG_TIMEOUT       20000
 #endif
 
-/* EEPROM */
-#ifdef CONFIG_ZYNQMP_EEPROM
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-# define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
-# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
-# define CONFIG_SYS_EEPROM_SIZE			(64 * 1024)
-#endif
-
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
 
 #define CONFIG_CLOCKS
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 94177c6..3ab783e 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -69,7 +69,7 @@
 # define CONFIG_THOR_RESET_OFF
 # define DFU_ALT_INFO_RAM \
 	"dfu_ram_info=" \
-	"set dfu_alt_info " \
+	"setenv dfu_alt_info " \
 	"${kernel_image} ram 0x3000000 0x500000\\\\;" \
 	"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
 	"${ramdisk_image} ram 0x2000000 0x600000\0" \
@@ -79,7 +79,7 @@
 # if defined(CONFIG_MMC_SDHCI_ZYNQ)
 #  define DFU_ALT_INFO_MMC \
 	"dfu_mmc_info=" \
-	"set dfu_alt_info " \
+	"setenv dfu_alt_info " \
 	"${kernel_image} fat 0 1\\\\;" \
 	"${devicetree_image} fat 0 1\\\\;" \
 	"${ramdisk_image} fat 0 1\0" \
@@ -227,9 +227,9 @@
 				"env run importbootenv; " \
 			"fi; " \
 		"fi; \0" \
-	"sd_loadbootenv=set bootenv_dev mmc && " \
+	"sd_loadbootenv=setenv bootenv_dev mmc && " \
 			"run setbootenv \0" \
-	"usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \
+	"usb_loadbootenv=setenv bootenv_dev usb && usb start && run setbootenv \0" \
 	"preboot=if test $modeboot = sdboot; then " \
 			"run sd_loadbootenv; " \
 			"echo Checking if uenvcmd is set ...; " \
diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h
new file mode 100644
index 0000000..25164d7
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-tcon-top.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+
+#define CLK_TCON_TOP_TV0	0
+#define CLK_TCON_TOP_TV1	1
+#define CLK_TCON_TOP_DSI	2
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
diff --git a/include/efi.h b/include/efi.h
index d98441a..3c9d20f 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -190,7 +190,7 @@
 #define EFI_MEM_DESC_VERSION	1
 
 #define EFI_PAGE_SHIFT		12
-#define EFI_PAGE_SIZE		(1UL << EFI_PAGE_SHIFT)
+#define EFI_PAGE_SIZE		(1ULL << EFI_PAGE_SHIFT)
 #define EFI_PAGE_MASK		(EFI_PAGE_SIZE - 1)
 
 struct efi_mem_desc {
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 00b81c6..f7bf732 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -344,6 +344,9 @@
 				 void *protocol_interface);
 /* Delete all protocols from a handle */
 efi_status_t efi_remove_all_protocols(const efi_handle_t handle);
+/* Install multiple protocol interfaces */
+efi_status_t EFIAPI efi_install_multiple_protocol_interfaces
+				(efi_handle_t *handle, ...);
 /* Call this to create an event */
 efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl,
 			      void (EFIAPI *notify_function) (
diff --git a/include/fpga.h b/include/fpga.h
index 195f0bd..51de5c5 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -41,7 +41,7 @@
 	unsigned int blocksize;
 	char *interface;
 	char *dev_part;
-	char *filename;
+	const char *filename;
 	int fstype;
 } fpga_fs_info;
 
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
index 4068de0..a6c1221 100644
--- a/include/usb/dwc2_udc.h
+++ b/include/usb/dwc2_udc.h
@@ -9,6 +9,7 @@
 #define __DWC2_USB_GADGET
 
 #define PHY0_SLEEP              (1 << 5)
+#define DWC2_MAX_HW_ENDPOINTS	16
 
 struct dwc2_plat_otg_data {
 	void		*priv;
@@ -22,8 +23,14 @@
 	unsigned int	rx_fifo_sz;
 	unsigned int	np_tx_fifo_sz;
 	unsigned int	tx_fifo_sz;
+	unsigned int	tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS];
+	unsigned char   tx_fifo_sz_nb;
+	bool		force_b_session_valid;
+	bool		activate_stm_id_vb_detection;
 };
 
 int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata);
 
+int dwc2_udc_B_session_valid(struct udevice *dev);
+
 #endif	/* __DWC2_USB_GADGET */
diff --git a/include/video.h b/include/video.h
index 1d57b48..485071d 100644
--- a/include/video.h
+++ b/include/video.h
@@ -70,6 +70,7 @@
  *		the LCD is updated
  * @cmap:	Colour map for 8-bit-per-pixel displays
  * @fg_col_idx:	Foreground color code (bit 3 = bold, bit 0-2 = color)
+ * @bg_col_idx:	Background color code (bit 3 = bold, bit 0-2 = color)
  */
 struct video_priv {
 	/* Things set up by the driver: */
@@ -92,6 +93,7 @@
 	bool flush_dcache;
 	ushort *cmap;
 	u8 fg_col_idx;
+	u8 bg_col_idx;
 };
 
 /* Placeholder - there are no video operations at present */
diff --git a/lib/efi_driver/efi_uclass.c b/lib/efi_driver/efi_uclass.c
index 7cdf81f..b14746e 100644
--- a/lib/efi_driver/efi_uclass.c
+++ b/lib/efi_driver/efi_uclass.c
@@ -300,9 +300,6 @@
 	struct driver *drv;
 	efi_status_t ret = EFI_SUCCESS;
 
-	/* Save 'gd' pointer */
-	efi_save_gd();
-
 	debug("EFI: Initializing EFI driver framework\n");
 	for (drv = ll_entry_start(struct driver, driver);
 	     drv < ll_entry_end(struct driver, driver); ++drv) {
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 23487b8..50b0501 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -26,6 +26,16 @@
 	  set, only the the correct handling of the letters of the codepage
 	  used by the FAT file system is ensured.
 
+config EFI_PLATFORM_LANG_CODES
+	string "Language codes supported by firmware"
+	depends on EFI_LOADER
+	default "en-US"
+	help
+	  This value is used to initialize the PlatformLangCodes variable. Its
+	  value is a semicolon (;) separated list of language codes in native
+	  RFC 4646 format, e.g. "en-US;de-DE". The first language code is used
+	  to initialize the PlatformLang variable.
+
 config EFI_LOADER_BOUNCE_BUFFER
 	bool "EFI Applications use bounce buffers for DMA operations"
 	depends on EFI_LOADER && ARM64
@@ -38,14 +48,11 @@
 config EFI_LOADER_HII
 	bool "Expose HII protocols to EFI applications"
 	depends on EFI_LOADER
-	default n
+	default y
 	help
 	  The Human Interface Infrastructure is a complicated framework that
 	  allows UEFI applications to draw fancy menus and hook strings using
 	  a translation framework.
 
 	  U-Boot implements enough of its features to be able to run the UEFI
-	  Shell, but not more than that. The code is experimental still, so
-	  beware that your system might break with HII enabled.
-
-	  If unsure, say n.
+	  Shell, but not more than that.
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index b215bd7..abc295e 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1569,26 +1569,6 @@
 	if (ret != EFI_SUCCESS)
 		goto failure;
 
-#if CONFIG_IS_ENABLED(EFI_LOADER_HII)
-	ret = efi_add_protocol(&obj->header,
-			       &efi_guid_hii_string_protocol,
-			       (void *)&efi_hii_string);
-	if (ret != EFI_SUCCESS)
-		goto failure;
-
-	ret = efi_add_protocol(&obj->header,
-			       &efi_guid_hii_database_protocol,
-			       (void *)&efi_hii_database);
-	if (ret != EFI_SUCCESS)
-		goto failure;
-
-	ret = efi_add_protocol(&obj->header,
-			       &efi_guid_hii_config_routing_protocol,
-			       (void *)&efi_hii_config_routing);
-	if (ret != EFI_SUCCESS)
-		goto failure;
-#endif
-
 	*info_ptr = info;
 	*handle_ptr = obj;
 
@@ -2287,7 +2267,7 @@
  *
  * Return: status code
  */
-static efi_status_t EFIAPI efi_install_multiple_protocol_interfaces
+efi_status_t EFIAPI efi_install_multiple_protocol_interfaces
 				(efi_handle_t *handle, ...)
 {
 	EFI_ENTRY("%p", handle);
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 53b40c8..d8c052d 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -5,8 +5,6 @@
  * (C) Copyright 2017 Rob Clark
  */
 
-#define LOG_CATEGORY LOGL_ERR
-
 #include <common.h>
 #include <blk.h>
 #include <dm.h>
@@ -970,7 +968,7 @@
 	if (!is_net) {
 		part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition,
 					       1);
-		if (part < 0)
+		if (part < 0 || !desc)
 			return EFI_INVALID_PARAMETER;
 
 		if (device)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index dbe29b8..46681dc 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -193,6 +193,7 @@
 			free(map);
 		} else {
 			map->desc.physical_start = carve_end;
+			map->desc.virtual_start = carve_end;
 			map->desc.num_pages = (map_end - carve_end)
 					      >> EFI_PAGE_SHIFT;
 		}
@@ -211,6 +212,7 @@
 	newmap = calloc(1, sizeof(*newmap));
 	newmap->desc = map->desc;
 	newmap->desc.physical_start = carve_start;
+	newmap->desc.virtual_start = carve_start;
 	newmap->desc.num_pages = (map_end - carve_start) >> EFI_PAGE_SHIFT;
 	/* Insert before current entry (descending address order) */
 	list_add_tail(&newmap->link, &map->link);
diff --git a/lib/efi_loader/efi_root_node.c b/lib/efi_loader/efi_root_node.c
index b056ba3..392f5c4 100644
--- a/lib/efi_loader/efi_root_node.c
+++ b/lib/efi_loader/efi_root_node.c
@@ -26,16 +26,10 @@
  */
 efi_status_t efi_root_node_register(void)
 {
-	efi_handle_t root;
-	efi_status_t ret;
+	efi_handle_t root = NULL;
 	struct efi_root_dp *dp;
 
-	/* Create handle */
-	ret = efi_create_handle(&root);
-	if (ret != EFI_SUCCESS)
-		return ret;
-
-	/* Install device path protocol */
+	/* Create device path protocol */
 	dp = calloc(1, sizeof(*dp));
 	if (!dp)
 		return EFI_OUT_OF_RESOURCES;
@@ -51,29 +45,29 @@
 	dp->end.sub_type = DEVICE_PATH_SUB_TYPE_END;
 	dp->end.length = sizeof(struct efi_device_path);
 
-	/* Install device path protocol */
-	ret = efi_add_protocol(root, &efi_guid_device_path, dp);
-	if (ret != EFI_SUCCESS)
-		goto failure;
-
-	/* Install device path to text protocol */
-	ret = efi_add_protocol(root, &efi_guid_device_path_to_text_protocol,
-			       (void *)&efi_device_path_to_text);
-	if (ret != EFI_SUCCESS)
-		goto failure;
-
-	/* Install device path utilities protocol */
-	ret = efi_add_protocol(root, &efi_guid_device_path_utilities_protocol,
-			       (void *)&efi_device_path_utilities);
-	if (ret != EFI_SUCCESS)
-		goto failure;
-
-	/* Install Unicode collation protocol */
-	ret = efi_add_protocol(root, &efi_guid_unicode_collation_protocol,
-			       (void *)&efi_unicode_collation_protocol);
-	if (ret != EFI_SUCCESS)
-		goto failure;
-
-failure:
-	return ret;
+	/* Create root node and install protocols */
+	return EFI_CALL(efi_install_multiple_protocol_interfaces(&root,
+		       /* Device path protocol */
+		       &efi_guid_device_path, dp,
+		       /* Device path to text protocol */
+		       &efi_guid_device_path_to_text_protocol,
+		       (void *)&efi_device_path_to_text,
+		       /* Device path utilities protocol */
+		       &efi_guid_device_path_utilities_protocol,
+		       (void *)&efi_device_path_utilities,
+		       /* Unicode collation protocol */
+		       &efi_guid_unicode_collation_protocol,
+		       (void *)&efi_unicode_collation_protocol,
+#if CONFIG_IS_ENABLED(EFI_LOADER_HII)
+		       /* HII string protocol */
+		       &efi_guid_hii_string_protocol,
+		       (void *)&efi_hii_string,
+		       /* HII database protocol */
+		       &efi_guid_hii_database_protocol,
+		       (void *)&efi_hii_database,
+		       /* HII configuration routing protocol */
+		       &efi_guid_hii_config_routing_protocol,
+		       (void *)&efi_hii_config_routing,
+#endif
+		       NULL));
 }
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index a908843..b32a7b3 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -10,34 +10,21 @@
 
 #define OBJ_LIST_NOT_INITIALIZED 1
 
-/* Language code for American English according to RFC 4646 */
-#define EN_US L"en-US"
-
 static efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
 
-/* Initialize and populate EFI object list */
-efi_status_t efi_init_obj_list(void)
+/**
+ * efi_init_platform_lang() - define supported languages
+ *
+ * Set the PlatformLangCodes and PlatformLang variables.
+ *
+ * Return:	status code
+ */
+static efi_status_t efi_init_platform_lang(void)
 {
-	efi_status_t ret = EFI_SUCCESS;
-
-	/*
-	 * On the ARM architecture gd is mapped to a fixed register (r9 or x18).
-	 * As this register may be overwritten by an EFI payload we save it here
-	 * and restore it on every callback entered.
-	 */
-	efi_save_gd();
-
-	/*
-	 * Variable PlatformLang defines the language that the machine has been
-	 * configured for.
-	 */
-	ret = EFI_CALL(efi_set_variable(L"PlatformLang",
-					&efi_global_variable_guid,
-					EFI_VARIABLE_BOOTSERVICE_ACCESS |
-					EFI_VARIABLE_RUNTIME_ACCESS,
-					sizeof(EN_US), EN_US));
-	if (ret != EFI_SUCCESS)
-		goto out;
+	efi_status_t ret;
+	efi_uintn_t data_size = 0;
+	char *lang = CONFIG_EFI_PLATFORM_LANG_CODES;
+	char *pos;
 
 	/*
 	 * Variable PlatformLangCodes defines the language codes that the
@@ -47,14 +34,62 @@
 					&efi_global_variable_guid,
 					EFI_VARIABLE_BOOTSERVICE_ACCESS |
 					EFI_VARIABLE_RUNTIME_ACCESS,
-					sizeof(EN_US), EN_US));
+					sizeof(CONFIG_EFI_PLATFORM_LANG_CODES),
+					CONFIG_EFI_PLATFORM_LANG_CODES));
 	if (ret != EFI_SUCCESS)
 		goto out;
 
+	/*
+	 * Variable PlatformLang defines the language that the machine has been
+	 * configured for.
+	 */
+	ret = EFI_CALL(efi_get_variable(L"PlatformLang",
+					&efi_global_variable_guid,
+					NULL, &data_size, &pos));
+	if (ret == EFI_BUFFER_TOO_SMALL) {
+		/* The variable is already set. Do not change it. */
+		ret = EFI_SUCCESS;
+		goto out;
+	}
+
+	/*
+	 * The list of supported languages is semicolon separated. Use the first
+	 * language to initialize PlatformLang.
+	 */
+	pos = strchr(lang, ';');
+	if (pos)
+		*pos = 0;
+
+	ret = EFI_CALL(efi_set_variable(L"PlatformLang",
+					&efi_global_variable_guid,
+					EFI_VARIABLE_NON_VOLATILE |
+					EFI_VARIABLE_BOOTSERVICE_ACCESS |
+					EFI_VARIABLE_RUNTIME_ACCESS,
+					1 + strlen(lang), lang));
+out:
+	if (ret != EFI_SUCCESS)
+		printf("EFI: cannot initialize platform language settings\n");
+	return ret;
+}
+
+/**
+ * efi_init_obj_list() - Initialize and populate EFI object list
+ *
+ * Return:	status code
+ */
+efi_status_t efi_init_obj_list(void)
+{
+	efi_status_t ret = EFI_SUCCESS;
+
 	/* Initialize once only */
 	if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED)
 		return efi_obj_list_initialized;
 
+	/* Define supported languages */
+	ret = efi_init_platform_lang();
+	if (ret != EFI_SUCCESS)
+		goto out;
+
 	/* Initialize system table */
 	ret = efi_initialize_system_table();
 	if (ret != EFI_SUCCESS)
diff --git a/lib/efi_selftest/efi_selftest_memory.c b/lib/efi_selftest/efi_selftest_memory.c
index 24b4438..5eeb42a 100644
--- a/lib/efi_selftest/efi_selftest_memory.c
+++ b/lib/efi_selftest/efi_selftest_memory.c
@@ -4,7 +4,7 @@
  *
  * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
  *
- * This unit test checks the following runtime services:
+ * This unit test checks the following boottime services:
  * AllocatePages, FreePages, GetMemoryMap
  *
  * The memory type used for the device tree is checked.
@@ -65,6 +65,11 @@
 	for (i = 0; map_size; ++i, map_size -= desc_size) {
 		struct efi_mem_desc *entry = &memory_map[i];
 
+		if (entry->physical_start != entry->virtual_start) {
+			efi_st_error("Physical and virtual addresses do not match\n");
+			return EFI_ST_FAILURE;
+		}
+
 		if (addr >= entry->physical_start &&
 		    addr < entry->physical_start +
 			    (entry->num_pages << EFI_PAGE_SHIFT)) {
@@ -171,9 +176,9 @@
 	/* Check memory reservation for the device tree */
 	if (fdt_addr &&
 	    find_in_memory_map(map_size, memory_map, desc_size, fdt_addr,
-			       EFI_RUNTIME_SERVICES_DATA) != EFI_ST_SUCCESS) {
+			       EFI_BOOT_SERVICES_DATA) != EFI_ST_SUCCESS) {
 		efi_st_error
-			("Device tree not marked as runtime services data\n");
+			("Device tree not marked as boot services data\n");
 		return EFI_ST_FAILURE;
 	}
 	return EFI_ST_SUCCESS;
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index fa98efc..421362d 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1555,8 +1555,6 @@
 CONFIG_QEMU_MIPS
 CONFIG_QIXIS_I2C_ACCESS
 CONFIG_QSPI
-CONFIG_QSPI_QUAD_SUPPORT
-CONFIG_QSPI_SEL_GPIO
 CONFIG_QUOTA
 CONFIG_R7780MP
 CONFIG_R8A66597_BASE_ADDR
@@ -1939,7 +1937,6 @@
 CONFIG_STV0991_HZ
 CONFIG_STV0991_HZ_CLOCK
 CONFIG_ST_SMI
-CONFIG_SUNXI_AHCI
 CONFIG_SUNXI_GPIO
 CONFIG_SUNXI_MAX_FB_SIZE
 CONFIG_SUPERH_ON_CHIP_R8A66597
@@ -4400,7 +4397,6 @@
 CONFIG_TIMESTAMP
 CONFIG_TIZEN
 CONFIG_TI_KSNAV
-CONFIG_TI_SPI_MMAP
 CONFIG_TMU_TIMER
 CONFIG_TPL_PAD_TO
 CONFIG_TPM_TIS_BASE_ADDRESS
@@ -4514,7 +4510,6 @@
 CONFIG_USB_EHCI_SPEAR
 CONFIG_USB_EHCI_TXFIFO_THRESH
 CONFIG_USB_EHCI_VCT
-CONFIG_USB_EHCI_VF
 CONFIG_USB_ETH_QMULT
 CONFIG_USB_ETH_SUBSET
 CONFIG_USB_EXT2_BOOT
@@ -4542,7 +4537,6 @@
 CONFIG_USB_INVENTRA_DMA
 CONFIG_USB_ISP1301_I2C_ADDR
 CONFIG_USB_MAX_CONTROLLER_COUNT
-CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 CONFIG_USB_MUSB_TIMEOUT
 CONFIG_USB_MUSB_TUSB6010
 CONFIG_USB_OHCI_EP93XX
diff --git a/test/py/tests/test_fpga.py b/test/py/tests/test_fpga.py
index 798f6ee..e3bb7b4 100644
--- a/test/py/tests/test_fpga.py
+++ b/test/py/tests/test_fpga.py
@@ -357,6 +357,19 @@
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('fit')
 @pytest.mark.buildconfigspec('cmd_echo')
+def test_fpga_loadmk_fit_external(u_boot_console):
+    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit_external')
+
+    u_boot_console.run_command('imi %x' % (addr))
+
+    expected_text = 'FPGA loaded successfully'
+    output = u_boot_console.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
+    assert expected_text in output
+
+@pytest.mark.buildconfigspec('cmd_fpga')
+@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
+@pytest.mark.buildconfigspec('fit')
+@pytest.mark.buildconfigspec('cmd_echo')
 def test_fpga_loadmk_fit(u_boot_console):
     f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')